公开(公告)号：US20050130439A1

公开(公告)日：2005-06-16

申请号：US11010223

申请日：2004-12-10

申请人： Juseon Goo ,  Eunkee Hong ,  Hong-Gun Kim ,  Kyu-Tae Na

发明人： Juseon Goo ,  Eunkee Hong ,  Hong-Gun Kim ,  Kyu-Tae Na

IPC分类号： H01L21/31 ,  H01L21/316 ,  H01L21/60 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/469

CPC分类号： H01L21/02164 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02318 ,  H01L21/316 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/76897

摘要： Methods of forming an insulating layer in a semiconductor device are provided in which a metal oxide layer is formed on a semiconductor structure that includes a plurality of gap regions thereon. A spin-on-glass layer is formed on the metal oxide layer, and then the semiconductor structure is heated to a temperature of at least about 400° C. The spin-on-glass layer may comprise a siloxane-based material, a silanol-based material or a silazane-based material.

摘要翻译： 提供了在半导体器件中形成绝缘层的方法，其中在其上包括多个间隙区域的半导体结构上形成金属氧化物层。 在金属氧化物层上形成旋涂玻璃层，然后将半导体结构加热到至少约400℃的温度。旋涂玻璃层可以包括基于硅氧烷的材料，硅烷醇 的材料或硅氮烷基材料。

公开(公告)号：US07585786B2

公开(公告)日：2009-09-08

申请号：US11010223

申请日：2004-12-10

申请人： Juseon Goo ,  Eunkee Hong ,  Hong-Gun Kim ,  Kyu-Tae Na

发明人： Juseon Goo ,  Eunkee Hong ,  Hong-Gun Kim ,  Kyu-Tae Na

IPC分类号： H01L21/31

CPC分类号： H01L21/02164 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02318 ,  H01L21/316 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/76897

摘要： Methods of forming an insulating layer in a semiconductor device are provided in which a metal oxide layer is formed on a semiconductor structure that includes a plurality of gap regions thereon. A spin-on-glass layer is formed on the metal oxide layer, and then the semiconductor structure is heated to a temperature of at least about 400° C. The spin-on-glass layer may comprise a siloxane-based material, a silanol-based material or a silazane-based material.

摘要翻译： 提供了在半导体器件中形成绝缘层的方法，其中在其上包括多个间隙区域的半导体结构上形成金属氧化物层。 在金属氧化物层上形成旋涂玻璃层，然后将半导体结构加热到至少约400℃的温度。旋涂玻璃层可以包括基于硅氧烷的材料，硅烷醇 的材料或硅氮烷基材料。

公开(公告)号：US20090012221A1

公开(公告)日：2009-01-08

申请号：US12194313

申请日：2008-08-19

申请人： Eunkee Hong ,  Kyu-Tae Na ,  Ju-Seon Goo ,  Hong-Gun Kim

发明人： Eunkee Hong ,  Kyu-Tae Na ,  Ju-Seon Goo ,  Hong-Gun Kim

IPC分类号： C08K5/06 ,  C08L83/08

CPC分类号： H01L21/3125 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/316 ,  H01L21/31695 ,  H01L21/76232 ,  H01L21/76837

摘要： A film is formed on a substrate including conductive patterns or trenches using a composition that included a solvent and perhydro-polysilazane having a weight average molecular weight of about 1,800 to 3,000 and a molecular weight distribution of more than about 2.2 to about 3.0. The film is changed into a silicon oxide film, and then an opening is formed through the silicon oxide film. A contact is formed in the opening by filling the opening with conductive material. The silicon oxide film of perhydro-polysilazane having low molecular weight becomes dense and uniform.

摘要翻译： 使用包含重量平均分子量约1,800至3,000且分子量分布大于约2.2至约3.0的溶剂和全氢化聚硅氮烷的组合物在包括导电图案或沟槽的基材上形成膜。 将膜变成氧化硅膜，然后通过氧化硅膜形成开口。 通过用导电材料填充开口在开口中形成接触。 具有低分子量的全氢聚硅氮烷的氧化硅膜变得致密且均匀。

公开(公告)号：US20060054989A1

公开(公告)日：2006-03-16

申请号：US11209879

申请日：2005-08-23

申请人： Hong-Gun Kim ,  Eunkee Hong ,  Kyu-Tae Na

发明人： Hong-Gun Kim ,  Eunkee Hong ,  Kyu-Tae Na

IPC分类号： C23C16/00

CPC分类号： C23C16/45523 ,  C23C16/045 ,  C23C16/401

摘要： A semiconductor device includes a first structure having a recess having a bottom and opposing side surfaces, and a second structure conformally disposed on the bottom and side surfaces of the recess. The second structure includes a multilayer having two layers having a thickness substantially smaller than a width of the recess. Methods of manufacturing a semiconductor device include providing a first structure having a recess in a deposition chamber and flowing first and second reactants over the first structure for a first period at first and second flow rates. Then, the flow rates of the first second reactants to the first structure are substantially reduced for a pause period. The first and second reactants are then flowed over the first structure for a second period at third and fourth flow rates. The deposition and pause steps may be repeated until a multilayer having a desired thickness is formed.

摘要翻译： 半导体器件包括具有底部和相对侧表面的凹部的第一结构以及保形地设置在凹部的底部和侧表面上的第二结构。 第二结构包括具有两个层的多层，其厚度基本上小于凹部的宽度。 制造半导体器件的方法包括提供在沉积室中具有凹槽的第一结构，并且使第一和第二反应物以第一和第二流速在第一结构上流动第一期间。 然后，第一第二反应物对第一结构的流速在暂停时间段内显着降低。 然后将第一和第二反应物以第三和第四流速在第一结构上流动第二时段。 可以重复沉积和暂停步骤，直到形成具有期望厚度的多层。

公开(公告)号：US07601588B2

公开(公告)日：2009-10-13

申请号：US11267360

申请日：2005-11-04

申请人： Jong-Wan Choi ,  Hong-Gun Kim ,  Kyu-Tae Na ,  Eunkee Hong

发明人： Jong-Wan Choi ,  Hong-Gun Kim ,  Kyu-Tae Na ,  Eunkee Hong

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/76232 ,  H01L27/115

摘要： In a method of forming a device isolation layer for minimizing a parasitic capacitor and a non-volatile memory device using the same, a trench is formed on a substrate. A first insulation layer is formed on a top surface of the substrate and on inner surfaces of the trench, so that the trench is partially filled with the first insulation layer. A second insulation layer is formed on the first insulation layer to a thickness to fill up the trench, thereby forming a preliminary isolation layer. An etching rate of the second insulation layer is different from that of the first insulation layer. A recess is formed at a central portion of the preliminary isolation layer by partially removing the first and second insulation layers, thereby forming the device isolation layer including the recess. The recess in the device isolation layer reduces a parasitic capacitance in a non-volatile memory device.

摘要翻译： 在形成用于最小化寄生电容器的器件隔离层和使用其的非易失性存储器件的方法中，在衬底上形成沟槽。 第一绝缘层形成在衬底的顶表面和沟槽的内表面上，使得沟槽部分地被第一绝缘层填充。 在第一绝缘层上形成第二绝缘层至填充沟槽的厚度，从而形成预备隔离层。 第二绝缘层的蚀刻速率与第一绝缘层的蚀刻速率不同。 通过部分去除第一绝缘层和第二绝缘层，在预隔离层的中心部分处形成凹部，从而形成包括凹部的器件隔离层。 器件隔离层中的凹槽降低了非易失性存储器件中的寄生电容。

公开(公告)号：US20060094203A1

公开(公告)日：2006-05-04

申请号：US11267360

申请日：2005-11-04

申请人： Jong-Wan Choi ,  Hong-Gun Kim ,  Kyu-Tae Na ,  Eunkee Hong

发明人： Jong-Wan Choi ,  Hong-Gun Kim ,  Kyu-Tae Na ,  Eunkee Hong

IPC分类号： H01L21/76

CPC分类号： H01L27/11521 ,  H01L21/76232 ,  H01L27/115

摘要： In a method of forming a device isolation layer for minimizing a parasitic capacitor and a non-volatile memory device using the same, a trench is formed on a substrate. A first insulation layer is formed on a top surface of the substrate and on inner surfaces of the trench, so that the trench is partially filled with the first insulation layer. A second insulation layer is formed on the first insulation layer to a thickness to fill up the trench, thereby forming a preliminary isolation layer. An etching rate of the second insulation layer is different from that of the first insulation layer. A recess is formed at a central portion of the preliminary isolation layer by partially removing the first and second insulation layers, thereby forming the device isolation layer including the recess. The recess in the device isolation layer reduces a parasitic capacitance in a non-volatile memory device.

公开(公告)号：US07534698B2

公开(公告)日：2009-05-19

申请号：US11209879

申请日：2005-08-23

申请人： Hong-Gun Kim ,  Eunkee Hong ,  Kyu-Tae Na

发明人： Hong-Gun Kim ,  Eunkee Hong ,  Kyu-Tae Na

IPC分类号： H01L21/76

CPC分类号： C23C16/45523 ,  C23C16/045 ,  C23C16/401

摘要： A semiconductor device includes a first structure having a recess having a bottom and opposing side surfaces, and a second structure conformally disposed on the bottom and side surfaces of the recess. The second structure includes a multilayer having two layers having a thickness substantially smaller than a width of the recess. Methods of manufacturing a semiconductor device include providing a first structure having a recess in a deposition chamber and flowing first and second reactants over the first structure for a first period at first and second flow rates. Then, the flow rates of the first second reactants to the first structure are substantially reduced for a pause period. The first and second reactants are then flowed over the first structure for a second period at third and fourth flow rates. The deposition and pause steps may be repeated until a multilayer having a desired thickness is formed.

摘要翻译： 半导体器件包括具有底部和相对侧表面的凹部的第一结构以及保形地设置在凹部的底部和侧表面上的第二结构。 第二结构包括具有两个层的多层，其厚度基本上小于凹部的宽度。 制造半导体器件的方法包括提供在沉积室中具有凹槽的第一结构，并且使第一和第二反应物以第一和第二流速在第一结构上流动第一期间。 然后，第一第二反应物对第一结构的流速在暂停时间段内显着降低。 然后将第一和第二反应物以第三和第四流速在第一结构上流动第二时段。 可以重复沉积和暂停步骤，直到形成具有期望厚度的多层。

公开(公告)号：US20060089008A1

公开(公告)日：2006-04-27

申请号：US11259408

申请日：2005-10-26

申请人： Eunkee Hong ,  Ju-Seon Goo ,  Kyu-Tae Na ,  Sang-Ho Rha

发明人： Eunkee Hong ,  Ju-Seon Goo ,  Kyu-Tae Na ,  Sang-Ho Rha

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76232 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/3125 ,  H01L21/316

摘要： Methods of manufacturing silicon oxide layers for semiconductor devices are provided in which a substrate having a recess is coated with a spin-on-glass film so that the recess is filled with the spin-on-glass film. A main thermal treatment is performed on the spin-on-glass film at about 600 to about 1,000° C. at about 1 ATM to about 50 ATM so that the spin-on-glass film is converted into a relatively dense silicon oxide layer.

摘要翻译： 提供了制造用于半导体器件的氧化硅层的方法，其中具有凹陷的衬底涂覆有旋涂玻璃膜，使得凹部填充有旋涂玻璃膜。 在旋转玻璃膜上进行主要的热处理，在约1 00至约1000℃，约1个ATM至约50个ATM处进行，以使旋涂玻璃膜转化成相对致密的氧化硅层。

公开(公告)号：US20050026443A1

公开(公告)日：2005-02-03

申请号：US10631848

申请日：2003-08-01

申请人： Ju-Seon Goo ,  Eun-Kee Hong ,  Hong-Gun Kim ,  Kyu-Tae Na

发明人： Ju-Seon Goo ,  Eun-Kee Hong ,  Hong-Gun Kim ,  Kyu-Tae Na

IPC分类号： H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/762 ,  H01L21/768 ,  H01L21/311

CPC分类号： H01L21/02222 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/02326 ,  H01L21/02343 ,  H01L21/3125 ,  H01L21/3165 ,  H01L21/76229 ,  H01L21/76826 ,  H01L21/76828

摘要： A method is provided for forming silicon oxide layers during the processing of semiconductor devices by applying a SOG layer including polysilazane to a substrate and then substantially converting the SOG layer to a silicon oxide layer using an oxidant solution. The oxidant solution may include one or more oxidants including, for example, ozone, peroxides, permanganates, hypochlorites, chlorites, chlorates, perchlorates, hypobromites, bromites, bromates, hypoiodites, iodites, iodates and strong acids.

摘要翻译： 提供了一种通过将包含聚硅氮烷的SOG层施加到衬底然后使用氧化剂溶液将SOG层基本上转化为氧化硅层来在半导体器件加工期间形成氧化硅层的方法。 氧化剂溶液可以包括一种或多种氧化剂，包括例如臭氧，过氧化物，高锰酸盐，次氯酸盐，亚氯酸盐，氯酸盐，高氯酸盐，次溴酸盐，溴酸盐，溴酸盐，次碘酸盐，碘酸盐，碘酸盐和强酸。

公开(公告)号：US20070020879A1

公开(公告)日：2007-01-25

申请号：US11484574

申请日：2006-07-12

申请人： Eun-Kyung Baek ,  Ju-Seon Goo ,  Mun-Jun Kim ,  Hong-Gun Kim ,  Kyu-Tae Na

发明人： Eun-Kyung Baek ,  Ju-Seon Goo ,  Mun-Jun Kim ,  Hong-Gun Kim ,  Kyu-Tae Na

IPC分类号： H01L21/8234 ,  H01L21/76 ,  H01L21/336

CPC分类号： H01L21/76229 ,  H01L29/66795 ,  H01L29/7851

摘要： In a method of forming a device isolation layer, a trench is formed in a substrate and a preliminary fin is formed on the substrate using a hard mask pattern on a surface of the substrate as an etching mask. A first thin layer is formed on the bottom and sides of the trench. A lower insulation pattern is formed in a lower portion of the trench on the first thin layer, and an upper insulation pattern is formed on the lower insulation pattern. The upper insulation pattern is etched away so that the first thin layer remains on a side surface of the preliminary fin. A device isolation layer is formed in the lower portion of the trench and a silicon fin is formed having a top surface thereof that is higher relative to a top surface of the device isolation layer.

摘要翻译： 在形成器件隔离层的方法中，在衬底中形成沟槽，并且使用在衬底的表面上的硬掩模图案作为蚀刻掩模在衬底上形成预备鳍。 第一薄层形成在沟槽的底部和侧面上。 在第一薄层上的沟槽的下部形成下部绝缘图案，并且在下部绝缘图案上形成上部绝缘图案。 蚀刻掉上绝缘图案，使得第一薄层保留在预备翅片的侧表面上。 器件隔离层形成在沟槽的下部，并且形成硅片，其顶表面相对于器件隔离层的顶表面较高。