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    Method of forming a trench isolation layer and method of manufacturing a non-volatile memory device using the same
    1.
    发明授权
    Method of forming a trench isolation layer and method of manufacturing a non-volatile memory device using the same 有权
    形成沟槽隔离层的方法和使用其形成非易失性存储器件的方法

    公开(公告)号：US07601588B2

    公开(公告)日：2009-10-13

    申请号：US11267360

    申请日：2005-11-04

    申请人： Jong-Wan Choi ,  Hong-Gun Kim ,  Kyu-Tae Na ,  Eunkee Hong

    发明人： Jong-Wan Choi ,  Hong-Gun Kim ,  Kyu-Tae Na ,  Eunkee Hong

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11521 ,  H01L21/76232 ,  H01L27/115

    摘要： In a method of forming a device isolation layer for minimizing a parasitic capacitor and a non-volatile memory device using the same, a trench is formed on a substrate. A first insulation layer is formed on a top surface of the substrate and on inner surfaces of the trench, so that the trench is partially filled with the first insulation layer. A second insulation layer is formed on the first insulation layer to a thickness to fill up the trench, thereby forming a preliminary isolation layer. An etching rate of the second insulation layer is different from that of the first insulation layer. A recess is formed at a central portion of the preliminary isolation layer by partially removing the first and second insulation layers, thereby forming the device isolation layer including the recess. The recess in the device isolation layer reduces a parasitic capacitance in a non-volatile memory device.

    摘要翻译： 在形成用于最小化寄生电容器的器件隔离层和使用其的非易失性存储器件的方法中，在衬底上形成沟槽。 第一绝缘层形成在衬底的顶表面和沟槽的内表面上，使得沟槽部分地被第一绝缘层填充。 在第一绝缘层上形成第二绝缘层至填充沟槽的厚度，从而形成预备隔离层。 第二绝缘层的蚀刻速率与第一绝缘层的蚀刻速率不同。 通过部分去除第一绝缘层和第二绝缘层，在预隔离层的中心部分处形成凹部，从而形成包括凹部的器件隔离层。 器件隔离层中的凹槽降低了非易失性存储器件中的寄生电容。

    Method of forming a trench isolation layer and method of manufacturing a non-volatile memory device using the same
    2.
    发明申请
    Method of forming a trench isolation layer and method of manufacturing a non-volatile memory device using the same 有权

    公开(公告)号：US20060094203A1

    公开(公告)日：2006-05-04

    申请号：US11267360

    申请日：2005-11-04

    申请人： Jong-Wan Choi ,  Hong-Gun Kim ,  Kyu-Tae Na ,  Eunkee Hong

    发明人： Jong-Wan Choi ,  Hong-Gun Kim ,  Kyu-Tae Na ,  Eunkee Hong

    IPC分类号： H01L21/76

    CPC分类号： H01L27/11521 ,  H01L21/76232 ,  H01L27/115

    摘要： In a method of forming a device isolation layer for minimizing a parasitic capacitor and a non-volatile memory device using the same, a trench is formed on a substrate. A first insulation layer is formed on a top surface of the substrate and on inner surfaces of the trench, so that the trench is partially filled with the first insulation layer. A second insulation layer is formed on the first insulation layer to a thickness to fill up the trench, thereby forming a preliminary isolation layer. An etching rate of the second insulation layer is different from that of the first insulation layer. A recess is formed at a central portion of the preliminary isolation layer by partially removing the first and second insulation layers, thereby forming the device isolation layer including the recess. The recess in the device isolation layer reduces a parasitic capacitance in a non-volatile memory device.

    Semiconductor devices having multilayer isolation structures and methods of forming semiconductor devices having multilayer isolation structures
    4.
    发明申请
    Semiconductor devices having multilayer isolation structures and methods of forming semiconductor devices having multilayer isolation structures 有权
    具有多层隔离结构的半导体器件和形成具有多层隔离结构的半导体器件的方法

    公开(公告)号：US20060054989A1

    公开(公告)日：2006-03-16

    申请号：US11209879

    申请日：2005-08-23

    申请人： Hong-Gun Kim ,  Eunkee Hong ,  Kyu-Tae Na

    发明人： Hong-Gun Kim ,  Eunkee Hong ,  Kyu-Tae Na

    IPC分类号： C23C16/00

    CPC分类号： C23C16/45523 ,  C23C16/045 ,  C23C16/401

    摘要： A semiconductor device includes a first structure having a recess having a bottom and opposing side surfaces, and a second structure conformally disposed on the bottom and side surfaces of the recess. The second structure includes a multilayer having two layers having a thickness substantially smaller than a width of the recess. Methods of manufacturing a semiconductor device include providing a first structure having a recess in a deposition chamber and flowing first and second reactants over the first structure for a first period at first and second flow rates. Then, the flow rates of the first second reactants to the first structure are substantially reduced for a pause period. The first and second reactants are then flowed over the first structure for a second period at third and fourth flow rates. The deposition and pause steps may be repeated until a multilayer having a desired thickness is formed.

    摘要翻译： 半导体器件包括具有底部和相对侧表面的凹部的第一结构以及保形地设置在凹部的底部和侧表面上的第二结构。 第二结构包括具有两个层的多层，其厚度基本上小于凹部的宽度。 制造半导体器件的方法包括提供在沉积室中具有凹槽的第一结构，并且使第一和第二反应物以第一和第二流速在第一结构上流动第一期间。 然后，第一第二反应物对第一结构的流速在暂停时间段内显着降低。 然后将第一和第二反应物以第三和第四流速在第一结构上流动第二时段。 可以重复沉积和暂停步骤，直到形成具有期望厚度的多层。

    Methods of forming semiconductor devices having multilayer isolation structures
    6.
    发明授权
    Methods of forming semiconductor devices having multilayer isolation structures 有权
    形成具有多层隔离结构的半导体器件的方法

    公开(公告)号：US07534698B2

    公开(公告)日：2009-05-19

    申请号：US11209879

    申请日：2005-08-23

    申请人： Hong-Gun Kim ,  Eunkee Hong ,  Kyu-Tae Na

    发明人： Hong-Gun Kim ,  Eunkee Hong ,  Kyu-Tae Na

    IPC分类号： H01L21/76

    CPC分类号： C23C16/45523 ,  C23C16/045 ,  C23C16/401

    摘要： A semiconductor device includes a first structure having a recess having a bottom and opposing side surfaces, and a second structure conformally disposed on the bottom and side surfaces of the recess. The second structure includes a multilayer having two layers having a thickness substantially smaller than a width of the recess. Methods of manufacturing a semiconductor device include providing a first structure having a recess in a deposition chamber and flowing first and second reactants over the first structure for a first period at first and second flow rates. Then, the flow rates of the first second reactants to the first structure are substantially reduced for a pause period. The first and second reactants are then flowed over the first structure for a second period at third and fourth flow rates. The deposition and pause steps may be repeated until a multilayer having a desired thickness is formed.

    摘要翻译： 半导体器件包括具有底部和相对侧表面的凹部的第一结构以及保形地设置在凹部的底部和侧表面上的第二结构。 第二结构包括具有两个层的多层，其厚度基本上小于凹部的宽度。 制造半导体器件的方法包括提供在沉积室中具有凹槽的第一结构，并且使第一和第二反应物以第一和第二流速在第一结构上流动第一期间。 然后，第一第二反应物对第一结构的流速在暂停时间段内显着降低。 然后将第一和第二反应物以第三和第四流速在第一结构上流动第二时段。 可以重复沉积和暂停步骤，直到形成具有期望厚度的多层。

    Method of forming an isolation layer and method of manufacturing a field effect transistor using the same
    9.
    发明申请
    Method of forming an isolation layer and method of manufacturing a field effect transistor using the same 审中-公开
    形成隔离层的方法和使用其形成场效应晶体管的方法

    公开(公告)号：US20070020879A1

    公开(公告)日：2007-01-25

    申请号：US11484574

    申请日：2006-07-12

    申请人： Eun-Kyung Baek ,  Ju-Seon Goo ,  Mun-Jun Kim ,  Hong-Gun Kim ,  Kyu-Tae Na

    发明人： Eun-Kyung Baek ,  Ju-Seon Goo ,  Mun-Jun Kim ,  Hong-Gun Kim ,  Kyu-Tae Na

    IPC分类号： H01L21/8234 ,  H01L21/76 ,  H01L21/336

    CPC分类号： H01L21/76229 ,  H01L29/66795 ,  H01L29/7851

    摘要： In a method of forming a device isolation layer, a trench is formed in a substrate and a preliminary fin is formed on the substrate using a hard mask pattern on a surface of the substrate as an etching mask. A first thin layer is formed on the bottom and sides of the trench. A lower insulation pattern is formed in a lower portion of the trench on the first thin layer, and an upper insulation pattern is formed on the lower insulation pattern. The upper insulation pattern is etched away so that the first thin layer remains on a side surface of the preliminary fin. A device isolation layer is formed in the lower portion of the trench and a silicon fin is formed having a top surface thereof that is higher relative to a top surface of the device isolation layer.

    摘要翻译： 在形成器件隔离层的方法中，在衬底中形成沟槽，并且使用在衬底的表面上的硬掩模图案作为蚀刻掩模在衬底上形成预备鳍。 第一薄层形成在沟槽的底部和侧面上。 在第一薄层上的沟槽的下部形成下部绝缘图案，并且在下部绝缘图案上形成上部绝缘图案。 蚀刻掉上绝缘图案，使得第一薄层保留在预备翅片的侧表面上。 器件隔离层形成在沟槽的下部，并且形成硅片，其顶表面相对于器件隔离层的顶表面较高。

    Method for forming a silicon oxide layer using spin-on glass
    10.
    发明申请
    Method for forming a silicon oxide layer using spin-on glass 有权
    使用旋涂玻璃形成氧化硅层的方法

    公开(公告)号：US20070117412A1

    公开(公告)日：2007-05-24

    申请号：US11656469

    申请日：2007-01-23

    申请人： Ju-seon Goo ,  Eun-kee Hong ,  Hong-Gun Kim ,  Kyu-tae Na

    发明人： Ju-seon Goo ,  Eun-kee Hong ,  Hong-Gun Kim ,  Kyu-tae Na

    IPC分类号： H01L21/31

    CPC分类号： H01L21/02222 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/02326 ,  H01L21/02343 ,  H01L21/3125 ,  H01L21/3165 ,  H01L21/76229 ,  H01L21/76826 ,  H01L21/76828

    摘要： A method is provided for forming silicon oxide layers during the processing of semiconductor devices by applying a SOG layer including polysilazane to a substrate and then substantially converting the SOG layer to a silicon oxide layer using an oxidant solution. The oxidant solution may include one or more oxidants including, for example, ozone, peroxides, permanganates, hypochlorites, chlorites, chlorates, perchlorates, hypobromites, bromites, bromates, hypoiodites, iodites, iodates and strong acids.

    摘要翻译： 提供了一种通过将包含聚硅氮烷的SOG层施加到衬底然后使用氧化剂溶液将SOG层基本上转化为氧化硅层来在半导体器件加工期间形成氧化硅层的方法。 氧化剂溶液可以包括一种或多种氧化剂，包括例如臭氧，过氧化物，高锰酸盐，次氯酸盐，亚氯酸盐，氯酸盐，高氯酸盐，次溴酸盐，溴酸盐，溴酸盐，次碘酸盐，碘酸盐，碘酸盐和强酸。