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    Method of depositing a diffusion barrier for copper interconnection applications
    3.
    发明授权
    Method of depositing a diffusion barrier for copper interconnection applications 有权
    沉积用于铜互连应用的扩散阻挡层的方法

    公开(公告)号：US06541374B1

    公开(公告)日：2003-04-01

    申请号：US09965471

    申请日：2001-09-26

    申请人： Tarek Suwwan de Felipe ,  Michal Danek ,  Erich Klawuhn ,  Ronald A. Powell

    发明人： Tarek Suwwan de Felipe ,  Michal Danek ,  Erich Klawuhn ,  Ronald A. Powell

    IPC分类号： H01L214763

    CPC分类号： H01L21/76844 ,  H01L21/28556 ,  H01L21/76813 ,  H01L21/76856

    摘要： The present invention pertains to methods for forming diffusion barrier layers in the context of integrated circuit fabrication. Methods of the invention allow selective deposition of a metal-nitride barrier layer material on a partially fabricated integrated circuit having exposed conductor and dielectric regions and conversion of the metal-nitride barrier material into an effective diffusion barrier layer having low via resistance. In a preferred method using TiN, differential morphology in a single barrier layer deposition is achieved by controlling CVD process conditions. It is believed that the absolute amount of TiN deposited on the conductor is not reduced, but the morphology of is changed so that there is little or no increase in the via resistance after barrier formation. The invention also pertains to novel integrated circuit structures resulting from application of the described methods.

    摘要翻译： 本发明涉及在集成电路制造的上下文中形成扩散阻挡层的方法。 本发明的方法允许在具有暴露的导体和电介质区域的部分制造的集成电路上选择性地沉积金属氮化物阻挡层材料，并且将金属氮化物阻挡材料转化成具有低通孔电阻的有效扩散阻挡层。 在使用TiN的优选方法中，通过控制CVD工艺条件来实现单个阻挡层沉积中的微分形态。 据信，沉积在导体上的TiN的绝对量不降低，但是形态发生变化，使得阻挡层形成后的通孔电阻几乎不增加或没有增加。 本发明还涉及由应用所述方法产生的新型集成电路结构。

    Method of depositing copper seed on semiconductor substrates
    4.
    发明授权
    Method of depositing copper seed on semiconductor substrates 有权
    在半导体衬底上沉积铜晶种的方法

    公开(公告)号：US06642146B1

    公开(公告)日：2003-11-04

    申请号：US10121949

    申请日：2002-04-10

    申请人： Robert Rozbicki ,  Michal Danek ,  Erich Klawuhn

    发明人： Robert Rozbicki ,  Michal Danek ,  Erich Klawuhn

    IPC分类号： H01L2144

    CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865

    摘要： The present invention pertains to methods for depositing a metal seed layer on a wafer substrate having a plurality of recessed features. Methods of the invention include at least two operations. A first portion of a seed layer is deposited such that metal ions impinge on the wafer substrate substantially perpendicular to the wafer substrate work surface. The first portion is characterized by heavy bottom coverage in the recessed features and minimal overhang on the apertures of the recessed features. A second portion of the metal seed layer is deposited with simultaneous re-sputter of at least part of the first portion that covers the bottom of the features. During re-sputter, part of the seed material on the bottom is redistributed to the sidewalls of the features. Seed layers of the invention have minimal overhang and excellent step coverage.

    摘要翻译： 本发明涉及在具有多个凹陷特征的晶片衬底上沉积金属晶种层的方法。 本发明的方法包括至少两个操作。 种子层的第一部分被沉积，使得金属离子基本上垂直于晶片衬底工作表面撞击在晶片衬底上。 第一部分的特征在于凹陷特征中的重底部覆盖和凹陷特征的孔上的最小突出。 沉积金属种子层的第二部分，同时重新溅射覆盖特征底部的第一部分的至少一部分。 在重新溅射期间，底部的种子材料的一部分重新分布到特征的侧壁。 本发明的种子层具有最小的悬垂和优异的阶梯覆盖。

    Method of depositing a diffusion barrier for copper interconnect applications
    6.
    发明授权
    Method of depositing a diffusion barrier for copper interconnect applications 有权
    沉积用于铜互连应用的扩散阻挡层的方法

    公开(公告)号：US06607977B1

    公开(公告)日：2003-08-19

    申请号：US09965472

    申请日：2001-09-26

    申请人： Robert Rozbicki ,  Michal Danek ,  Erich Klawuhn

    发明人： Robert Rozbicki ,  Michal Danek ,  Erich Klawuhn

    IPC分类号： H01L214763

    CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865

    摘要： The present invention pertains to methods for forming a metal diffusion barrier on an integrated circuit wherein the formation includes at least two operations. The first operation deposits barrier material via PVD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. The result of the operations is a metal diffusion barrier formed in part by net etching in certain areas, in particular the bottom of vias, and a net deposition in other areas, in particular the side walls of vias. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects.

    摘要翻译： 本发明涉及在集成电路上形成金属扩散阻挡层的方法，其中形成包括至少两个操作。 第一个操作通过PVD或CVD沉积阻挡材料以提供一些最小的覆盖。 第二操作沉积另外的阻挡材料，同时蚀刻在第一操作中沉积的阻挡材料的一部分。 操作的结果是部分地通过在某些区域中的网蚀刻形成的金属扩散屏障，特别是通孔的底部，以及在其它区域，特别是通孔的侧壁中的净沉积。 使用受控蚀刻来选择性地从通孔底部去除屏障材料，完全或部分地去除，从而降低随后形成的金属互连的电阻。

    Deposition of conformal copper seed layers by control of barrier layer morphology
    7.
    发明授权
    Deposition of conformal copper seed layers by control of barrier layer morphology 有权
    通过控制阻挡层形态沉积保形铜种子层

    公开(公告)号：US06566246B1

    公开(公告)日：2003-05-20

    申请号：US09862539

    申请日：2001-05-21

    申请人： Tarek Suwwan de Felipe ,  Michal Danek ,  Erich Klawuhn ,  Alexander Dulkin

    发明人： Tarek Suwwan de Felipe ,  Michal Danek ,  Erich Klawuhn ,  Alexander Dulkin

    IPC分类号： H01L214763

    CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76846 ,  H01L21/76873 ,  H01L2221/1089

    摘要： The present invention pertains to systems and methods for improving the deposition of conformal copper seed layers in integrated circuit metalization. The invention involves controlling the morphology of the barrier layer deposited underneath the copper seed layer. The barrier layer can be composed of TaN and Ta, or TaN alone. It can also be composed of TiN or TiNSi. The process conditions of the barrier layer deposition are carried out in a manner that results in a highly or completely amorphous crystalline structure. Such a barrier layer allows for conformal deposition of the copper seed layer on top of the barrier layer that is less susceptible to agglomeration.

    摘要翻译： 本发明涉及在集成电路金属化中改进共形铜种子层的沉积的系统和方法。 本发明涉及控制沉积在铜籽晶层下面的势垒层的形态。 阻挡层可以由TaN和Ta或单独的TaN组成。 也可以由TiN或TiNSi组成。 阻挡层沉积的工艺条件以导致高度或完全无定形晶体结构的方式进行。 这种阻挡层允许铜籽晶层在不易凝聚的阻挡层顶部上保形沉积。

    Method of cleansing vias in semiconductor wafer having metal conductive layer
    8.
    发明授权
    Method of cleansing vias in semiconductor wafer having metal conductive layer 有权
    在具有金属导电层的半导体晶片中清洁通孔的方法

    公开(公告)号：US06319842B1

    公开(公告)日：2001-11-20

    申请号：US09753432

    申请日：2001-01-02

    申请人： Mukul Khosla ,  Lap Tam ,  Ronald A. Powell ,  Ronald D. Allen ,  Robert T. Rozbicki ,  Erich Klawuhn ,  E. Derryck Settles

    发明人： Mukul Khosla ,  Lap Tam ,  Ronald A. Powell ,  Ronald D. Allen ,  Robert T. Rozbicki ,  Erich Klawuhn ,  E. Derryck Settles

    IPC分类号： H01L21302

    CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/76814 ,  Y10S438/906

    摘要： Non-volatile and oxide residues that form during semiconductor processing are removed from the semiconductor structure in a two-stage process. An inert gas and a reducing gas are introduced to the reactor. In the first stage, the non-volatile contaminants are sputtered from the semiconductor structure by creating a plasma to ionize the inert gas. The power applied to the plasma is preferably high enough to give the ions of the inert gas a high degree of directionality as they approach the structure. The first stage is continued until the non-volatile contaminants have been sufficiently removed from the structure. In the second stage, the power is reduced and the reducing gas (e.g., hydrogen) reacts with the oxides (e.g., copper oxide) to form elemental metal and water vapor. During the second stage there is no appreciable sputtering, and therefore the damage to the structure is limited as compared with processes that use sputtering and reduction simultaneously.

    摘要翻译： 在半导体处理中形成的非挥发性和氧化物残余物在两阶段工艺中从半导体结构中去除。 将惰性气体和还原气体引入反应器。 在第一阶段，通过产生等离子体以使惰性气体离子化，从半导体结构溅射非挥发性污染物。 施加到等离子体的功率优选地足够高以使惰性气体的离子在接近结构时具有高度的方向性。 第一阶段继续进行，直至非挥发性污染物从结构中充分除去。 在第二阶段中，功率降低，并且还原气体（例如氢气）与氧化物（例如氧化铜）反应以形成元素金属和水蒸气。 在第二阶段期间，没有明显的溅射，因此与使用溅射和还原的方法相比，对结构的损害是有限的。