公开(公告)号：US06653226B1

公开(公告)日：2003-11-25

申请号：US09758307

申请日：2001-01-09

申请人： Jonathan David Reid

发明人： Jonathan David Reid

IPC分类号： H01L214763

CPC分类号： C25F3/16 ,  B23H5/08 ,  H01L21/7684

摘要： Methods and apparatus are used for electrochemical planarization of an electrically conductive material surface with varying topography from a partially fabricated integrated circuit, in which protruding regions of the conductive material are removed more quickly than recessed regions to thereby increase the planarity of the conductive material surface. This is accomplished by using dissolution electrochemistry. The partially fabricated integrated circuit is used as the anode in an electrochemical cell, with the anode and cathode active surfaces positioned in very close proximity. By using highly resistive electrolyte and moving the anode and cathode progressively closer during electrochemical dissolution, the electrically conductive material surface is effectively planarized.

摘要翻译： 方法和装置用于从部分制造的集成电路变化的导电材料表面进行电化学平面化，其中导电材料的突出区域比凹陷区域更快地去除，从而增加导电材料表面的平面度。 这是通过使用溶解电化学完成的。 部分制造的集成电路用作电化学电池中的阳极，其中阳极和阴极活性表面非常接近。 通过使用高电阻电解质并且在电化学溶解期间使阳极和阴极逐渐移动更接近，导电材料表面被有效地平坦化。

公开(公告)号：US06179983B2

公开(公告)日：2001-01-30

申请号：US08969267

申请日：1997-11-13

申请人： Jonathan David Reid ,  Steve Taatjes

发明人： Jonathan David Reid ,  Steve Taatjes

IPC分类号： C25D500

CPC分类号： C25D7/123 ,  C25D17/001 ,  C25D17/007 ,  C25D17/12 ,  Y10S204/07

摘要： An apparatus for depositing an electrical conductive layer on the surface of a wafer includes a virtual anode located between the actual anode and the wafer. The virtual anode modifies the electric current flux and plating solution flow between the actual anode and the wafer to thereby modify the thickness profile of the deposited electrically conductive layer on the wafer. The virtual anode can have openings through which the electrical current flux passes. By selectively varying the radius, length, or both, of the openings, any desired thickness profile of the deposited electrically conductive layer on the wafer can be readily obtained.

摘要翻译： 用于在晶片表面上沉积导电层的装置包括位于实际阳极和晶片之间的虚拟阳极。 虚拟阳极改变实际阳极和晶片之间的电流通量和电镀液流动，从而改变晶片上沉积的导电层的厚度分布。 虚拟阳极可以具有电流通过的开口。 通过选择性地改变开口的半径，长度或两者，可以容易地获得晶片上沉积的导电层的任何期望的厚度分布。

公开(公告)号：US6126798A

公开(公告)日：2000-10-03

申请号：US969196

申请日：1997-11-13

申请人： Jonathan David Reid ,  Robert J. Contolini ,  John Owen Dukovic

发明人： Jonathan David Reid ,  Robert J. Contolini ,  John Owen Dukovic

IPC分类号： C25D7/12 ,  C25D17/00 ,  C25D17/10 ,  C25B13/00

CPC分类号： C25D17/10 ,  C25D17/00 ,  C25D17/001 ,  C25D17/008

摘要： An anode includes an anode cup, a membrane and ion source material, the anode cup and membrane forming an enclosure in which the ion source material is located. The anode cup includes a base section having a central aperture and the membrane also has a central aperture. A jet is passed through the central apertures of the base section of the anode cup and through the membrane allowing plating solution to be directed at the center of a wafer being electroplated.

摘要翻译： 阳极包括阳极杯，膜和离子源材料，阳极杯和膜形成离子源材料所在的外壳。 阳极杯包括具有中心孔的基部，并且膜还具有中心孔。 射流穿过阳极杯的基部的中心孔并通过膜，允许电镀溶液指向正在电镀的晶片的中心。

公开(公告)号：US06569299B1

公开(公告)日：2003-05-27

申请号：US09574666

申请日：2000-05-18

申请人： Jonathan David Reid ,  Robert J. Contolini ,  John Owen Dukovic

发明人： Jonathan David Reid ,  Robert J. Contolini ,  John Owen Dukovic

IPC分类号： C25B1300

CPC分类号： C25D17/10 ,  C25D17/00 ,  C25D17/001 ,  C25D17/008

摘要： An anode includes an anode cup, a membrane and ion source material, the anode cup and membrane forming an enclosure in which the ion source material is located. The anode cup includes a base section having a central aperture and the membrane also has a central aperture. A jet is passed through the central apertures of the base section of the anode cup and through the membrane allowing plating solution to be directed at the center of a wafer being electroplated.

摘要翻译： 阳极包括阳极杯，膜和离子源材料，阳极杯和膜形成离子源材料所在的外壳。 阳极杯包括具有中心孔的基部，并且膜还具有中心孔。 射流穿过阳极杯的基部的中心孔并通过膜，允许电镀溶液指向正在电镀的晶片的中心。

公开(公告)号：US06284121B1

公开(公告)日：2001-09-04

申请号：US09354285

申请日：1999-07-15

申请人： Jonathan David Reid

发明人： Jonathan David Reid

IPC分类号： C25D500

CPC分类号： C25D3/38 ,  H05K3/423

摘要： An electroplating system includes a standard electroplating apparatus using an acid copper bath with an additive for leveling. The additive is chosen to have molecules of a size that is about the size of the features to be filled by the electroplating process. The relatively large size of these additive molecules tends to hinder the mass transfer of the additive molecules into the features. Consequently, the additive molecules are preferentially absorbed by the surface of the plating surface relative to the inner surfaces of the features. Accordingly, the electroplating process tends to fill the features relatively quickly compared to the other parts of the target surface so that all of the surface area of the target is equivalent in height. Because little or no additive molecules are within the features, the features tend to be filled without the voids often produced using conventional systems.

摘要翻译： 电镀系统包括使用酸性铜浴的标准电镀装置和用于流平的添加剂。 添加剂被选择为具有大约由电镀工艺填充的特征尺寸的分子。 这些添加剂分子的相对大尺寸倾向于妨碍添加剂分子进入特征的传质。 因此，添加剂分子相对于特征的内表面优先被电镀表面表面吸收。 因此，与目标表面的其他部分相比，电镀工艺倾向于相对快速地填充特征，使得靶的所有表面积的高度相当。 因为特征内部几乎没有或没有添加剂分子，所以特征倾向于被填充而没有常规系统常常产生的空隙。

公开(公告)号：US5731547A

公开(公告)日：1998-03-24

申请号：US603629

申请日：1996-02-20

申请人： Mark Daniel Derwin ,  Daniel Peter Labzentis ,  Jonathan David Reid ,  Timothy Lee Sharp

发明人： Mark Daniel Derwin ,  Daniel Peter Labzentis ,  Jonathan David Reid ,  Timothy Lee Sharp

IPC分类号： H01L21/56 ,  H01L23/12 ,  H01L23/24 ,  H05K1/00 ,  H05K3/24 ,  H05K3/28 ,  H05K3/40 ,  H05K1/09

CPC分类号： H01L23/24 ,  H05K3/28 ,  H01L2924/0002 ,  H05K1/0393 ,  H05K2201/09781 ,  H05K3/244 ,  H05K3/4007

摘要： A circuitized substrate having conductive circuitry thereon and a barrier located adjacent at least portions of the circuitry to serve as an effective constraint for liquid material (e.g., encapsulant) applied to cover and protect the circuitry. The barrier can be formed concurrently with circuitry formation and formed of materials (e.g., copper, nickel, gold) similar to those used for the circuitry. The barrier is of two-part construction and of a particular shape wherein one part affords a greater surface tension than the other such that the material may actually lie on one part while being prevented from engagement with the other. Providing such dual (or "progressive") surface tensions successfully constrains the liquid material at least until solidification thereof occurs.

摘要翻译： 电路基板，其上具有导电电路，以及位于电路的至少部分附近的阻挡层，用作用于覆盖和保护电路的液体材料（例如，密封剂）的有效约束。 阻挡层可以与电路形成同时形成，并且由类似于用于电路的材料（例如铜，镍，金）形成。 屏障是两部分构造和特定形状，其中一个部分提供比另一个部分更大的表面张力，使得材料实际上可以位于一个部分上，同时防止与另一个接合。 提供这种双重（或“渐进的”）表面张力成功地限制液体材料至少直到发生其固化。

公开(公告)号：US06554914B1

公开(公告)日：2003-04-29

申请号：US09776704

申请日：2001-02-02

申请人： Robert T. Rozbicki ,  Ronald Allan Powell ,  Erich Klawuhn ,  Michal Danek ,  Karl B. Levy ,  Jonathan David Reid ,  Mukul Khosla ,  Eliot K. Broadbent

发明人： Robert T. Rozbicki ,  Ronald Allan Powell ,  Erich Klawuhn ,  Michal Danek ,  Karl B. Levy ,  Jonathan David Reid ,  Mukul Khosla ,  Eliot K. Broadbent

IPC分类号： C23C824

CPC分类号： C23C8/10 ,  C23C8/02 ,  C23C8/34

摘要： The present invention pertains to systems and methods for passivating the copper seed layer deposited in Damascene integrated circuit manufacturing. More specifically, the invention pertains to systems and methods for depositing the copper seed layer by physical vapor deposition, while passivating the copper during or immediately after the deposition in order to prevent excessive oxidation of the copper. The invention is applicable to dual Damascene processing.

摘要翻译： 本发明涉及用于以镶嵌集成电路制造方式钝化沉积铜晶种层的系统和方法。 更具体地，本发明涉及用于通过物理气相沉积沉积铜籽晶层的系统和方法，同时在沉积期间或之后钝化铜，以防止铜的过度氧化。 本发明适用于双镶嵌加工。

公开(公告)号：US06458262B1

公开(公告)日：2002-10-01

申请号：US09802490

申请日：2001-03-09

申请人： Jonathan David Reid

发明人： Jonathan David Reid

IPC分类号： C25D2114

CPC分类号： C25D21/14

摘要： The present invention provides methods and apparatus for analysis and monitoring of electrolyte bath composition. Based on analysis results, the invention controls electrolyte bath composition and plating hardware. Thus, the invention provides control of electroplating processes based on plating bath composition data. The invention accomplishes this by incorporating accurate bath component analysis data into a feedback control mechanism for electroplating. Bath electrolyte is treated and analyzed in a flow-through system in order to identify plating bath component concentrations and based on the results, the plating bath formulation and plating process are controlled.

摘要翻译： 本发明提供了用于分析和监测电解液浴组合物的方法和装置。 基于分析结果，本发明控制电解液浴组成和电镀硬件。 因此，本发明提供了基于电镀浴组成数据的电镀工艺的控制。 本发明通过将精确的浴组分分析数据结合到用于电镀的反馈控制机构中来实现。 在流通系统中处理和分析浴电解质以鉴定电镀浴组分浓度，并且基于结果，控制电镀浴配方和电镀过程。

公开(公告)号：US6024857A

公开(公告)日：2000-02-15

申请号：US947222

申请日：1997-10-08

申请人： Jonathan David Reid

发明人： Jonathan David Reid

IPC分类号： C25D3/38 ,  H05K3/42 ,  C25D7/12

CPC分类号： C25D3/38 ,  H05K3/423

摘要： An electroplating system includes a standard electroplating apparatus using an acid copper bath with an additive for leveling. The additive is chosen to have molecules of a size that is about the size of the features to be filled by the electroplating process. The relatively large size of these additive molecules tends to hinder the mass transfer of the additive molecules into the features. Consequently, the additive molecules are preferentially absorbed by the surface of the plating surface relative to the inner surfaces of the features. Accordingly, the electroplating process tends to fill the features relatively quickly compared to the other parts of the target surface so that all of the surface area of the target is equivalent in height. Because little or no additive molecules are within the features, the features tend to be filled without the voids often produced using conventional systems.

摘要翻译： 电镀系统包括使用酸性铜浴的标准电镀装置和用于流平的添加剂。 添加剂被选择为具有大约由电镀工艺填充的特征尺寸的分子。 这些添加剂分子的相对大尺寸倾向于妨碍添加剂分子进入特征的传质。 因此，添加剂分子相对于特征的内表面优先被电镀表面表面吸收。 因此，与目标表面的其他部分相比，电镀工艺倾向于相对快速地填充特征，使得靶的所有表面积的高度相当。 因为特征内部几乎没有或没有添加剂分子，所以特征倾向于被填充而没有常规系统常常产生的空隙。

公开(公告)号：US5766499A

公开(公告)日：1998-06-16

申请号：US638251

申请日：1996-04-26

申请人： Kim Joseph Blackwell ,  Daniel Peter Labzentis ,  Jonathan David Reid

发明人： Kim Joseph Blackwell ,  Daniel Peter Labzentis ,  Jonathan David Reid

IPC分类号： H01L21/48 ,  H05K1/02 ,  H05K3/00 ,  H05K3/06 ,  H05K3/24 ,  H05K3/30 ,  H05K3/40 ,  H05K3/42 ,  H01L21/02

CPC分类号： H05K3/002 ,  H01L21/4857 ,  H05K1/0266 ,  H05K3/4007 ,  H05K2201/0166 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/09063 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2203/0554 ,  H05K2203/1476 ,  H05K2203/167 ,  H05K3/0008 ,  H05K3/062 ,  H05K3/243 ,  H05K3/303 ,  H05K3/427

摘要： A method of making a circuitized substrate wherein a dielectric layer is provided having a first layer of metallic material thereon. A first metallic member is formed on the dielectric's metallic layer, following which a pair of openings are precisely provided within a second dielectric material located on the dielectric. These openings in turn define a selected area on the first metallic member and, significantly, a precisely oriented pattern of the first metallic layer at a spaced distance from the metallic member. This metallic pattern serves as a mask to permit formation of an opening through the dielectric, which opening in turn may be engaged by tooling or the like such as may be used to position an electronic component, e.g., semiconductor device, on the underlying substrate. The invention thus assures precise orientation and placement of components such as semiconductor devices on highly dense circuit patterns such as those required in the present art in the manufacture of devices such as those of the information handling system (computer) variety.

摘要翻译： 一种制造电路化基板的方法，其中提供介电层，其上具有第一层金属材料。 第一金属构件形成在电介质的金属层上，随后在位于电介质上的第二电介质材料内精确地设置一对开口。 这些开口依次限定第一金属构件上的选定区域，并且显着地限定第一金属层与金属构件隔开距离的精确定向图案。 该金属图案用作掩模以允许通过电介质形成开口，该开口又可以通过工具等接合，例如可用于将电子部件（例如半导体器件）定位在下面的基板上。 因此，本发明确保了诸如半导体器件之类的部件在诸如本领域所需要的诸如信息处理系统（计算机）品种的设备的制造中的高密度电路图案上的精确取向和放置。