公开(公告)号：US09099474B2

公开(公告)日：2015-08-04

申请号：US13706530

申请日：2012-12-06

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Yoshihiro Uozumi

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L23/535 ,  H01L29/417 ,  H01L29/66 ,  H01L21/285 ,  H01L23/485 ,  H01L21/768 ,  H01L29/78

CPC分类号： H01L29/7845 ,  H01L21/28518 ,  H01L21/76814 ,  H01L23/485 ,  H01L23/535 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to certain embodiments, a silicide layer is formed after the fabrication of a functional gate electrode using a gate-last scheme. An initial semiconductor structure has at least one impurity regions formed on a semiconductor substrate, a sacrifice film formed over the impurity region, an isolation layer formed over the sacrifice film and a dielectric layer formed over the isolation film. A via is patterned into the dielectric layer of the initial semiconductor structure and through the thickness of the isolation layer such that a contact opening is formed in the isolation layer. The sacrifice film underlying the isolation layer is then removed leaving a void space underlying the isolation layer. Then, a metal silicide precursor is placed within the void space, and the metal silicide precursor is converted to a silicide layer through an annealing process.

摘要翻译： 根据某些实施例，在使用栅极 - 最后方案制造功能栅电极之后形成硅化物层。 初始半导体结构具有在半导体衬底上形成的至少一个杂质区，在杂质区上形成的牺牲膜，在牺牲膜上形成的隔离层和形成在隔离膜上的电介质层。 将通孔图案化到初始半导体结构的电介质层中并通过隔离层的厚度，使得在隔离层中形成接触开口。 然后去除隔离层下面的牺牲膜，留下隔离层下面的空隙。 然后，在空隙空间内放置金属硅化物前体，通过退火工艺将金属硅化物前体转化为硅化物层。

公开(公告)号：US20140061752A1

公开(公告)日：2014-03-06

申请号：US13848294

申请日：2013-03-21

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Seiichi Omoto ,  Yoshihiro Uozumi ,  Tadashi Iguchi ,  Osamu Yamane ,  Kazuyuki Masukawa ,  Yoshihiro Yanai

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66666 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7889 ,  H01L29/7926

摘要： According to one embodiment, a method for manufacturing a semiconductor device includes forming a stacked body on a substrate. The stacked body includes a plurality of first conductive layers including a metallic element as a main component and a plurality of second conductive layers including a metallic element as a main component provided respectively between the first conductive layers. The method includes making a hole to pierce the stacked body. The method includes making a slit to divide the stacked body. The method includes making a gap between the first conductive layers by removing the second conductive layers by etching via the slit or the hole. The method includes forming a memory film including a charge storage film at a side wall of the hole. The method includes forming a channel body on an inner side of the memory film inside the hole.

摘要翻译： 根据一个实施例，一种用于制造半导体器件的方法包括在衬底上形成层叠体。 所述层叠体包括多个第一导电层，所述第一导电层包含以金属元素为主要成分的多个第二导电层，以及分别设置在所述第一导电层之间的包含金属元素作为主要成分的多个第二导电层。 该方法包括形成一个孔以刺穿层叠体。 该方法包括制作狭缝以分开堆叠体。 该方法包括通过经由狭缝或孔的蚀刻去除第二导电层来在第一导电层之间形成间隙。 该方法包括在孔的侧壁形成包括电荷存储膜的记忆膜。 该方法包括在孔内的记忆膜的内侧形成通道体。

公开(公告)号：US09553189B2

公开(公告)日：2017-01-24

申请号：US14754079

申请日：2015-06-29

申请人： Kabushiki Kaisha Toshiba

发明人： Yoshihiro Uozumi

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L29/78 ,  H01L23/535 ,  H01L29/417 ,  H01L29/66 ,  H01L21/285 ,  H01L23/485 ,  H01L21/768

CPC分类号： H01L29/7845 ,  H01L21/28518 ,  H01L21/76814 ,  H01L23/485 ,  H01L23/535 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to certain embodiments, a silicide layer is formed after the fabrication of a functional gate electrode using a gate-last scheme. An initial semiconductor structure has at least one impurity regions formed on a semiconductor substrate, a sacrifice film formed over the impurity region, an isolation layer formed over the sacrifice film and a dielectric layer formed over the isolation film. A via is patterned into the dielectric layer of the initial semiconductor structure and through the thickness of the isolation layer such that a contact opening is formed in the isolation layer. The sacrifice film underlying the isolation layer is then removed leaving a void space underlying the isolation layer. Then, a metal silicide precursor is placed within the void space, and the metal silicide precursor is converted to a silicide layer through an annealing process.

摘要翻译： 根据某些实施例，在使用栅极 - 最后方案制造功能栅电极之后形成硅化物层。 初始半导体结构具有在半导体衬底上形成的至少一个杂质区，在杂质区上形成的牺牲膜，在牺牲膜上形成的隔离层和形成在隔离膜上的电介质层。 将通孔图案化到初始半导体结构的电介质层中并通过隔离层的厚度，使得在隔离层中形成接触开口。 然后去除隔离层下面的牺牲膜，留下隔离层下面的空隙。 然后，在空隙空间内放置金属硅化物前体，通过退火工艺将金属硅化物前体转化为硅化物层。

公开(公告)号：US20150318395A1

公开(公告)日：2015-11-05

申请号：US14754079

申请日：2015-06-29

申请人： Kabushiki Kaisha Toshiba

发明人： Yoshihiro Uozumi

IPC分类号： H01L29/78 ,  H01L23/535

CPC分类号： H01L29/7845 ,  H01L21/28518 ,  H01L21/76814 ,  H01L23/485 ,  H01L23/535 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to certain embodiments, a silicide layer is formed after the fabrication of a functional gate electrode using a gate-last scheme. An initial semiconductor structure has at least one impurity regions formed on a semiconductor substrate, a sacrifice film formed over the impurity region, an isolation layer formed over the sacrifice film and a dielectric layer formed over the isolation film. A via is patterned into the dielectric layer of the initial semiconductor structure and through the thickness of the isolation layer such that a contact opening is formed in the isolation layer. The sacrifice film underlying the isolation layer is then removed leaving a void space underlying the isolation layer. Then, a metal silicide precursor is placed within the void space, and the metal silicide precursor is converted to a silicide layer through an annealing process.

摘要翻译： 根据某些实施例，在使用栅极 - 最后方案制造功能栅电极之后形成硅化物层。 初始半导体结构具有在半导体衬底上形成的至少一个杂质区，在杂质区上形成的牺牲膜，在牺牲膜上形成的隔离层和形成在隔离膜上的电介质层。 将通孔图案化到初始半导体结构的电介质层中并通过隔离层的厚度，使得在隔离层中形成接触开口。 然后去除隔离层下面的牺牲膜，留下隔离层下面的空隙。 然后，在空隙空间内放置金属硅化物前体，通过退火工艺将金属硅化物前体转化为硅化物层。

公开(公告)号：US08912089B2

公开(公告)日：2014-12-16

申请号：US13848294

申请日：2013-03-21

申请人： Kabushiki Kaisha Toshiba

发明人： Seiichi Omoto ,  Yoshihiro Uozumi ,  Tadashi Iguchi ,  Osamu Yamane ,  Kazuyuki Masukawa ,  Yoshihiro Yanai

IPC分类号： H01L21/4763 ,  H01L27/115 ,  H01L29/792 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

CPC分类号： H01L29/66666 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7889 ,  H01L29/7926

摘要： According to one embodiment, a method for manufacturing a semiconductor device includes forming a stacked body on a substrate. The stacked body includes a plurality of first conductive layers including a metallic element as a main component and a plurality of second conductive layers including a metallic element as a main component provided respectively between the first conductive layers. The method includes making a hole to pierce the stacked body. The method includes making a slit to divide the stacked body. The method includes making a gap between the first conductive layers by removing the second conductive layers by etching via the slit or the hole. The method includes forming a memory film including a charge storage film at a side wall of the hole. The method includes forming a channel body on an inner side of the memory film inside the hole.

摘要翻译： 根据一个实施例，一种用于制造半导体器件的方法包括在衬底上形成层叠体。 所述层叠体包括多个第一导电层，所述第一导电层包含以金属元素为主要成分的多个第二导电层，以及分别设置在所述第一导电层之间的包含金属元素作为主要成分的多个第二导电层。 该方法包括形成一个孔以刺穿层叠体。 该方法包括制作狭缝以分开堆叠体。 该方法包括通过经由狭缝或孔的蚀刻去除第二导电层来在第一导电层之间形成间隙。 该方法包括在孔的侧壁形成包括电荷存储膜的记忆膜。 该方法包括在孔内的记忆膜的内侧形成通道体。

公开(公告)号：US20160071747A1

公开(公告)日：2016-03-10

申请号：US14940186

申请日：2015-11-13

申请人： Kabushiki Kaisha Toshiba

发明人： Yoshihiro Uozumi ,  Shinsuke Kimura ,  Yoshihiro Ogawa ,  Hiroyasu limori ,  Tatsuhiko Koide ,  Hideaki Hirabayashi ,  Yuji Nagashima

IPC分类号： H01L21/67 ,  H01L21/68 ,  H01L21/677

摘要： According to one embodiment, a substrate processing method is disclosed. The method can include treating a substrate with a first liquid. The substrate has a structural body formed on a major surface of the substrate. The method can include forming a support member supporting the structural body by bringing a second liquid into contact with the substrate wetted by the first liquid, and changing at least a portion of the second liquid into a solid by carrying out at least one of causing the second liquid to react, reducing a quantity of a solvent included in the second liquid, and causing at least a portion of a substance dissolved in the second liquid to be separated. The method can include removing the support member by changing at least a part of the support member from a solid phase to a gaseous phase, without passing through a liquid phase.

公开(公告)号：US08946809B2

公开(公告)日：2015-02-03

申请号：US14017472

申请日：2013-09-04

申请人： Kabushiki Kaisha Toshiba

发明人： Kazuhide Takamura ,  Ryota Katsumata ,  Masaru Kidoh ,  Yoshihiro Uozumi ,  Daigo Ichinose ,  Toru Matsuda

IPC分类号： H01L29/792 ,  G11C11/34 ,  H01L21/8236 ,  H01L29/66 ,  H01L21/822 ,  H01L27/12

CPC分类号： H01L29/66833 ,  H01L21/8221 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/1214 ,  H01L29/792 ,  H01L29/7926

摘要： According to one embodiment, a method is disclosed for manufacturing a semiconductor memory device. The method includes forming a first stopper film forming a lower gate layer, making a recess in the lower gate layer, filling a sacrificial film into the recess, forming a second stopper film, making an opening in the second stopper film, forming a stacked body. The stacked body includes electrode films and insulating films. The method includes, making a slit in the stacked body, making a hole in the stacked body, removing the sacrificial film via the hole, forming a memory film including a charge storage film. The method includes forming a channel body on a side wall of the memory film. An etching rate of the first stopper film and the second stopper film is lower than an etching rate of the electrode films and the insulating films.

摘要翻译： 根据一个实施例，公开了一种用于制造半导体存储器件的方法。 该方法包括形成形成下栅极层的第一阻挡膜，在下栅极层中形成凹陷，将牺牲膜填充到凹部中，形成第二阻挡膜，在第二阻挡膜中形成开口，形成层叠体 。 堆叠体包括电极膜和绝缘膜。 该方法包括：在堆叠体中形成狭缝，在堆叠体中形成孔，经由孔去除牺牲膜，形成包括电荷存储膜的记忆膜。 该方法包括在存储膜的侧壁上形成通道体。 第一阻挡膜和第二阻挡膜的蚀刻速率低于电极膜和绝缘膜的蚀刻速率。

公开(公告)号：US20140284691A1

公开(公告)日：2014-09-25

申请号：US14017472

申请日：2013-09-04

申请人： Kabushiki Kaisha Toshiba

发明人： Kazuhide Takamura ,  Ryota Katsumata ,  Masaru Kidoh ,  Yoshihiro Uozumi ,  Daigo Ichinose ,  Toru Matsuda

IPC分类号： H01L29/66 ,  H01L29/792

CPC分类号： H01L29/66833 ,  H01L21/8221 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/1214 ,  H01L29/792 ,  H01L29/7926

摘要： According to one embodiment, a method is disclosed for manufacturing a semiconductor memory device. The method includes forming a first stopper film forming a lower gate layer, making a recess in the lower gate layer, filling a sacrificial film into the recess, forming a second stopper film, making an opening in the second stopper film, forming a stacked body. The stacked body includes electrode films and insulating films. The method includes, making a slit in the stacked body, making a hole in the stacked body, removing the sacrificial film via the hole, forming a memory film including a charge storage film. The method includes forming a channel body on a side wall of the memory film. An etching rate of the first stopper film and the second stopper film is lower than an etching rate of the electrode films and the insulating films.

摘要翻译： 根据一个实施例，公开了一种用于制造半导体存储器件的方法。 该方法包括形成形成下栅极层的第一阻挡膜，在下栅极层中形成凹陷，将牺牲膜填充到凹部中，形成第二阻挡膜，在第二阻挡膜中形成开口，形成层叠体 。 堆叠体包括电极膜和绝缘膜。 该方法包括：在堆叠体中形成狭缝，在堆叠体中形成孔，经由孔去除牺牲膜，形成包括电荷存储膜的记忆膜。 该方法包括在存储膜的侧壁上形成通道体。 第一阻挡膜和第二阻挡膜的蚀刻速率低于电极膜和绝缘膜的蚀刻速率。