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1.发明授权Exposure tolerance estimation method and method for manufacturing semiconductor device 有权曝光容差估计方法及半导体装置的制造方法公开(公告)号：US08956791B2
公开(公告)日：2015-02-17
申请号：US14027353
申请日：2013-09-16
发明人： Osamu Yamane , Kazuyuki Masukawa , Yasunobu Kai
IPC分类号： G03F7/20
CPC分类号： G03F7/20 , G03F7/70625 , G03F7/70641
摘要： According to one embodiment, an exposure tolerance estimation method is disclosed. The method can include setting a plurality of regions along a first surface of a substrate. The method can form a plurality of patterns for estimation by performing exposure on each of the regions using at least three levels of exposure condition using an exposure mask. The method can measure dimensions of the patterns for estimation and find relationships between the exposure condition and the dimensions. The method can select a first region from the regions. In the first region, a first dimension of a first pattern for estimation formed by exposure using a first exposure condition of an intermediate level out of the at least three levels falls within a previously set range. In addition, the method can calculate an exposure tolerance from a relationship between the first exposure condition and the first dimension.
摘要翻译： 根据一个实施例，公开了一种曝光容限估计方法。 该方法可以包括沿着衬底的第一表面设置多个区域。 该方法可以通过使用曝光掩模使用至少三个曝光条件的水平来对每个区域进行曝光来形成用于估计的多个图案。 该方法可以测量用于估计的图案的尺寸并且找到曝光条件和尺寸之间的关系。 该方法可以从区域中选择第一区域。 在第一区域中，通过使用在至少三个级别中的中间级别的第一曝光条件的曝光形成的用于估计的第一图案的第一尺寸落在预先设定的范围内。 此外，该方法可以根据第一曝光条件和第一尺寸之间的关系来计算曝光公差。
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公开(公告)号：US20140061752A1
公开(公告)日：2014-03-06
申请号：US13848294
申请日：2013-03-21
发明人： Seiichi Omoto , Yoshihiro Uozumi , Tadashi Iguchi , Osamu Yamane , Kazuyuki Masukawa , Yoshihiro Yanai
CPC分类号： H01L29/66666 , H01L27/11565 , H01L27/11575 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7827 , H01L29/7889 , H01L29/7926
摘要： According to one embodiment, a method for manufacturing a semiconductor device includes forming a stacked body on a substrate. The stacked body includes a plurality of first conductive layers including a metallic element as a main component and a plurality of second conductive layers including a metallic element as a main component provided respectively between the first conductive layers. The method includes making a hole to pierce the stacked body. The method includes making a slit to divide the stacked body. The method includes making a gap between the first conductive layers by removing the second conductive layers by etching via the slit or the hole. The method includes forming a memory film including a charge storage film at a side wall of the hole. The method includes forming a channel body on an inner side of the memory film inside the hole.
摘要翻译： 根据一个实施例，一种用于制造半导体器件的方法包括在衬底上形成层叠体。 所述层叠体包括多个第一导电层，所述第一导电层包含以金属元素为主要成分的多个第二导电层，以及分别设置在所述第一导电层之间的包含金属元素作为主要成分的多个第二导电层。 该方法包括形成一个孔以刺穿层叠体。 该方法包括制作狭缝以分开堆叠体。 该方法包括通过经由狭缝或孔的蚀刻去除第二导电层来在第一导电层之间形成间隙。 该方法包括在孔的侧壁形成包括电荷存储膜的记忆膜。 该方法包括在孔内的记忆膜的内侧形成通道体。
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3.发明授权Method for manufacturing a semiconductor device including a stacked body comprising pluralities of first and second metallic conductive layers 有权一种半导体器件的制造方法，包括具有多个第一和第二金属导电层的层叠体公开(公告)号：US08912089B2
公开(公告)日：2014-12-16
申请号：US13848294
申请日：2013-03-21
发明人： Seiichi Omoto , Yoshihiro Uozumi , Tadashi Iguchi , Osamu Yamane , Kazuyuki Masukawa , Yoshihiro Yanai
IPC分类号： H01L21/4763 , H01L27/115 , H01L29/792 , H01L29/66 , H01L29/78 , H01L29/788
CPC分类号： H01L29/66666 , H01L27/11565 , H01L27/11575 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7827 , H01L29/7889 , H01L29/7926
摘要： According to one embodiment, a method for manufacturing a semiconductor device includes forming a stacked body on a substrate. The stacked body includes a plurality of first conductive layers including a metallic element as a main component and a plurality of second conductive layers including a metallic element as a main component provided respectively between the first conductive layers. The method includes making a hole to pierce the stacked body. The method includes making a slit to divide the stacked body. The method includes making a gap between the first conductive layers by removing the second conductive layers by etching via the slit or the hole. The method includes forming a memory film including a charge storage film at a side wall of the hole. The method includes forming a channel body on an inner side of the memory film inside the hole.
摘要翻译： 根据一个实施例，一种用于制造半导体器件的方法包括在衬底上形成层叠体。 所述层叠体包括多个第一导电层，所述第一导电层包含以金属元素为主要成分的多个第二导电层，以及分别设置在所述第一导电层之间的包含金属元素作为主要成分的多个第二导电层。 该方法包括形成一个孔以刺穿层叠体。 该方法包括制作狭缝以分开堆叠体。 该方法包括通过经由狭缝或孔的蚀刻去除第二导电层来在第一导电层之间形成间隙。 该方法包括在孔的侧壁形成包括电荷存储膜的记忆膜。 该方法包括在孔内的记忆膜的内侧形成通道体。
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公开(公告)号：US20140242498A1
公开(公告)日：2014-08-28
申请号：US14013213
申请日：2013-08-29
发明人： Yuko Kono , Kazuyuki Masukawa , Toshiya Kotani , Chikaaki Kodama , Yasunobu Kai
摘要： According to one embodiment, a production method for a mask layout of an exposure mask includes evaluating a candidate layout by comparison between an imaged image group and a reference image group. The imaged image group is composed of a plurality of imaged images of patterns formed by performing lithography under a plurality of levels of exposure condition using the candidate layout. The reference image group is composed of a plurality of reference images produced by simulation on assumption of a plurality of levels of the exposure condition.
摘要翻译： 根据一个实施例，用于曝光掩模的掩模布局的制造方法包括通过成像图像组和参考图像组之间的比较来评估候选布局。 成像图像组由通过使用候选布局在多个曝光条件下执行光刻而形成的图案的多个成像图像组成。 参考图像组由假设多个曝光条件的水平的模拟产生的多个参考图像组成。
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5.发明申请PROCESS CONVERSION DIFFERENCE PREDICTION DEVICE, PROCESS CONVERSION DIFFERENCE PREDICTION METHOD, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM CONTAINING A PROCESS CONVERSION DIFFERENCE PREDICTION PROGRAM 审中-公开过程转换差分预测装置，过程转换差分预测方法和包含过程转换差异预测程序的非终端计算机可读记录介质公开(公告)号：US20150220846A1
公开(公告)日：2015-08-06
申请号：US14288523
申请日：2014-05-28
发明人： Ai INOUE , Minoru Inomoto , Kazuyuki Masukawa , Koutarou Sho , Seiro Miyoshi , Satoshi Usui
CPC分类号： G06F17/50 , G03F1/36 , G03F7/00 , G03F7/70433 , G03F7/705 , G03F7/70625
摘要： According to one embodiment, a process conversion difference in a processed pattern having undergone a process via the resist pattern can be predicted, based on results of simulation of a cross-sectional shape of the resist pattern by which predicted values of resist dimensions adapted to a relationship between a parameter for lithography and actual measurement values of the resist dimensions.
摘要翻译： 根据一个实施例，可以基于抗蚀剂图案的横截面形状的模拟结果来预测经历抗蚀剂图案的处理的处理图案中的工艺转换差异，通过该结果，抗蚀剂尺寸的预测值适应于 用于光刻的参数与抗蚀剂尺寸的实际测量值之间的关系。
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6.发明授权Integrated circuit device, method for producing mask layout, and program for producing mask layout 有权集成电路装置，制造掩模布局的方法以及用于制作掩模布局的程序公开(公告)号：US09257367B2
公开(公告)日：2016-02-09
申请号：US13969823
申请日：2013-08-19
发明人： Motohiro Okada , Shuhei Sota , Takaki Hashimoto , Yasunobu Kai , Kazuyuki Masukawa , Yuko Kono , Chikaaki Kodama , Taiga Uno , Hiromitsu Mashita
CPC分类号： H01L23/48 , G03F1/70 , G06F17/5081 , G06F19/00 , G06F2217/12 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a method for producing a mask layout of an exposure mask for forming wiring of an integrated circuit device, includes estimating shape of the wiring formed based on an edge of a pattern included in an initial layout of the exposure mask. The method includes modifying shape of the edge if the estimated shape of the wiring does not satisfy a requirement.
摘要翻译： 根据一个实施例，一种用于形成用于形成集成电路器件的布线的曝光掩模的掩模布局的方法包括基于包含在曝光掩模的初始布局中的图案的边缘来估计形成的布线的形状。 如果布线的估计形状不满足要求，则该方法包括修改边缘的形状。
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公开(公告)号：US09086634B2
公开(公告)日：2015-07-21
申请号：US14013213
申请日：2013-08-29
发明人： Yuko Kono , Kazuyuki Masukawa , Toshiya Kotani , Chikaaki Kodama , Yasunobu Kai
摘要： According to one embodiment, a production method for a mask layout of an exposure mask includes evaluating a candidate layout by comparison between an imaged image group and a reference image group. The imaged image group is composed of a plurality of imaged images of patterns formed by performing lithography under a plurality of levels of exposure condition using the candidate layout. The reference image group is composed of a plurality of reference images produced by simulation on assumption of a plurality of levels of the exposure condition.
摘要翻译： 根据一个实施例，用于曝光掩模的掩模布局的制造方法包括通过成像图像组和参考图像组之间的比较来评估候选布局。 成像图像组由通过使用候选布局在多个曝光条件下执行光刻而形成的图案的多个成像图像组成。 参考图像组由假设多个曝光条件的水平的模拟产生的多个参考图像组成。
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8.发明申请EXPOSURE TOLERANCE ESTIMATION METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权接触耐久性估算方法和制造半导体器件的方法公开(公告)号：US20140287350A1
公开(公告)日：2014-09-25
申请号：US14027353
申请日：2013-09-16
发明人： Osamu YAMANE , Kazuyuki Masukawa , Yasunobu Kai
IPC分类号： G03F7/20
CPC分类号： G03F7/20 , G03F7/70625 , G03F7/70641
摘要： According to one embodiment, an exposure tolerance estimation method is disclosed. The method can include setting a plurality of regions along a first surface of a substrate. The method can form a plurality of patterns for estimation by performing exposure on each of the regions using at least three levels of exposure condition using an exposure mask. The method can measure dimensions of the patterns for estimation and find relationships between the exposure condition and the dimensions. The method can select a first region from the regions. In the first region, a first dimension of a first pattern for estimation formed by exposure using a first exposure condition of an intermediate level out of the at least three levels falls within a previously set range. In addition, the method can calculate an exposure tolerance from a relationship between the first exposure condition and the first dimension.
摘要翻译： 根据一个实施例，公开了一种曝光容限估计方法。 该方法可以包括沿着衬底的第一表面设置多个区域。 该方法可以通过使用曝光掩模使用至少三个曝光条件的水平来对每个区域进行曝光来形成用于估计的多个图案。 该方法可以测量用于估计的图案的尺寸并且找到曝光条件和尺寸之间的关系。 该方法可以从区域中选择第一区域。 在第一区域中，通过使用在至少三个级别中的中间级别的第一曝光条件的曝光形成的用于估计的第一图案的第一尺寸落在预先设定的范围内。 此外，该方法可以根据第一曝光条件和第一尺寸之间的关系来计算曝光公差。
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