公开(公告)号：US20140061752A1

公开(公告)日：2014-03-06

申请号：US13848294

申请日：2013-03-21

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Seiichi Omoto ,  Yoshihiro Uozumi ,  Tadashi Iguchi ,  Osamu Yamane ,  Kazuyuki Masukawa ,  Yoshihiro Yanai

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66666 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7889 ,  H01L29/7926

摘要： According to one embodiment, a method for manufacturing a semiconductor device includes forming a stacked body on a substrate. The stacked body includes a plurality of first conductive layers including a metallic element as a main component and a plurality of second conductive layers including a metallic element as a main component provided respectively between the first conductive layers. The method includes making a hole to pierce the stacked body. The method includes making a slit to divide the stacked body. The method includes making a gap between the first conductive layers by removing the second conductive layers by etching via the slit or the hole. The method includes forming a memory film including a charge storage film at a side wall of the hole. The method includes forming a channel body on an inner side of the memory film inside the hole.

摘要翻译： 根据一个实施例，一种用于制造半导体器件的方法包括在衬底上形成层叠体。 所述层叠体包括多个第一导电层，所述第一导电层包含以金属元素为主要成分的多个第二导电层，以及分别设置在所述第一导电层之间的包含金属元素作为主要成分的多个第二导电层。 该方法包括形成一个孔以刺穿层叠体。 该方法包括制作狭缝以分开堆叠体。 该方法包括通过经由狭缝或孔的蚀刻去除第二导电层来在第一导电层之间形成间隙。 该方法包括在孔的侧壁形成包括电荷存储膜的记忆膜。 该方法包括在孔内的记忆膜的内侧形成通道体。

公开(公告)号：US09543321B1

公开(公告)日：2017-01-10

申请号：US14991084

申请日：2016-01-08

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Kazuaki Nakajima ,  Seiichi Omoto ,  Hiroshi Toyoda

IPC分类号： H01L27/11 ,  H01L27/115 ,  H01L29/792 ,  H01L29/66 ,  H01L21/311 ,  H01L21/28

CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L21/31116 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792

摘要： A semiconductor memory device according to an embodiment comprises a stacked body, a semiconductor layer, a charge accumulation layer, and a slit portion. The stacked body includes a plurality of control gate electrodes stacked above a substrate. The semiconductor layer has one end thereof connected to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. The slit portion extends in a direction of the substrate from a surface of the stacked body, wherein the slit portion has its longitudinal direction in a direction intersecting the first direction.

摘要翻译： 根据实施例的半导体存储器件包括层叠体，半导体层，电荷累积层和狭缝部。 堆叠体包括层叠在基板上方的多个控制栅电极。 半导体层的一端与基板连接，面对多个控制栅电极。 电荷累积层位于控制栅电极和半导体层之间。 所述狭缝部从所述层叠体的表面向所述基板的方向延伸，所述狭缝部的长度方向与所述第一方向相交。

公开(公告)号：US20170062286A1

公开(公告)日：2017-03-02

申请号：US15014718

申请日：2016-02-03

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Kazumasa ITO ,  Seiichi Omoto ,  Takanobu Itoh ,  Ryota Nakanishi

IPC分类号： H01L21/66 ,  H01L27/115 ,  C23C16/52 ,  H01L21/768 ,  H01L23/532 ,  C23C16/06 ,  H01L23/522 ,  H01L21/28

CPC分类号： H01L22/26 ,  C23C16/045 ,  C23C16/06 ,  C23C16/52 ,  H01L21/76879 ,  H01L27/1157 ,  H01L27/11582

摘要： A semiconductor manufacturing method according to an embodiment includes forming a first film on a semiconductor substrate. The semiconductor manufacturing method includes forming cavities in the first film. The semiconductor manufacturing method includes forming a second film inside the cavities by a CVD method using first gas containing a component of the second film, detecting a first time point at which the second film blocks openings of the cavities in forming the second film, and ending forming of the second film at a second time point at which a predetermined time has elapsed from the first time point.

摘要翻译： 根据实施例的半导体制造方法包括在半导体衬底上形成第一膜。 半导体制造方法包括在第一膜中形成空腔。 半导体制造方法包括通过使用包含第二膜的成分的第一气体的CVD法在空腔内形成第二膜，检测第二膜在阻挡形成第二膜的空腔的开口的第一时间点，并且结束 在从第一时间点经过预定时间的第二时间点形成第二胶卷。

公开(公告)号：US09514977B2

公开(公告)日：2016-12-06

申请号：US14200636

申请日：2014-03-07

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Toshiyuki Morita ,  Seiichi Omoto ,  Kazuaki Nakajima ,  Hiroshi Toyoda

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L27/115 ,  H01L21/288

CPC分类号： H01L21/768 ,  H01L21/288 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L27/11531 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to the present embodiment includes a first wiring part located above a substrate and made of a first metal material. A second wiring part is provided as being superimposed on the first wiring part and having a width substantially equal to that of the first wiring part. A first resistivity of the first wiring part is lower than a second resistivity of the second wiring part when the first and second wiring parts have a first width. The second resistivity is lower than the first resistivity when the first and second wiring parts have a second width larger than the first width. The semiconductor device includes both of an area in which the first and second wiring parts have the first width and an area in which the first and second wiring parts have the second width.

摘要翻译： 根据本实施例的半导体器件包括位于基板上方并由第一金属材料制成的第一布线部分。 第二配线部分被叠置在第一布线部分上并具有与第一布线部分的宽度基本相等的宽度。 当第一和第二布线部分具有第一宽度时，第一布线部分的第一电阻率低于第二布线部分的第二电阻率。 当第一和第二布线部分具有大于第一宽度的第二宽度时，第二电阻率低于第一电阻率。 半导体器件包括第一和第二布线部分具有第一宽度的区域和第一和第二布线部分具有第二宽度的区域。

公开(公告)号：US08912089B2

公开(公告)日：2014-12-16

申请号：US13848294

申请日：2013-03-21

申请人： Kabushiki Kaisha Toshiba

发明人： Seiichi Omoto ,  Yoshihiro Uozumi ,  Tadashi Iguchi ,  Osamu Yamane ,  Kazuyuki Masukawa ,  Yoshihiro Yanai

IPC分类号： H01L21/4763 ,  H01L27/115 ,  H01L29/792 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

CPC分类号： H01L29/66666 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7889 ,  H01L29/7926

摘要： According to one embodiment, a method for manufacturing a semiconductor device includes forming a stacked body on a substrate. The stacked body includes a plurality of first conductive layers including a metallic element as a main component and a plurality of second conductive layers including a metallic element as a main component provided respectively between the first conductive layers. The method includes making a hole to pierce the stacked body. The method includes making a slit to divide the stacked body. The method includes making a gap between the first conductive layers by removing the second conductive layers by etching via the slit or the hole. The method includes forming a memory film including a charge storage film at a side wall of the hole. The method includes forming a channel body on an inner side of the memory film inside the hole.

摘要翻译： 根据一个实施例，一种用于制造半导体器件的方法包括在衬底上形成层叠体。 所述层叠体包括多个第一导电层，所述第一导电层包含以金属元素为主要成分的多个第二导电层，以及分别设置在所述第一导电层之间的包含金属元素作为主要成分的多个第二导电层。 该方法包括形成一个孔以刺穿层叠体。 该方法包括制作狭缝以分开堆叠体。 该方法包括通过经由狭缝或孔的蚀刻去除第二导电层来在第一导电层之间形成间隙。 该方法包括在孔的侧壁形成包括电荷存储膜的记忆膜。 该方法包括在孔内的记忆膜的内侧形成通道体。