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    Methods of forming p-channel field effect transistors having SiGe source/drain regions
    3.
    发明授权
    Methods of forming p-channel field effect transistors having SiGe source/drain regions 有权
    形成具有SiGe源极/漏极区域的p沟道场效应晶体管的方法

    公开(公告)号：US08198194B2

    公开(公告)日：2012-06-12

    申请号：US12729486

    申请日：2010-03-23

    申请人： Jong Ho Yang ,  Hyung-rae Lee ,  Jin-Ping Han ,  Chung Woh Lai ,  Henry K. Utomo ,  Thomas W. Dyer

    发明人： Jong Ho Yang ,  Hyung-rae Lee ,  Jin-Ping Han ,  Chung Woh Lai ,  Henry K. Utomo ,  Thomas W. Dyer

    IPC分类号： H01L21/311

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

    摘要： Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrificial sidewall spacer layer on the gate electrode. A mask layer then patterned on the gate electrode. The sacrificial sidewall spacer layer is selectively etched to define sacrificial sidewall spacers on the first sidewall spacers, using the patterned mask layer as an etching mask. A PFET halo-implant of dopants is then performed into portions of the semiconductor substrate that extend adjacent the gate electrode, using the sacrificial sidewall spacers as an implant mask. Following this implant step, source and drain region trenches are etched into the semiconductor substrate, on opposite sides of the gate electrode. These source and drain region trenches are then filled by epitaxially growing SiGe source and drain regions therein.

    摘要翻译： 形成p沟道MOSFET的方法使用在制造过程中相对较早执行的光晕注入步骤。 这些方法包括在半导体衬底上形成其上具有第一侧壁间隔物的栅电极，然后在栅电极上形成牺牲侧壁间隔层。 然后在栅电极上图案化掩模层。 选择性地蚀刻牺牲侧壁间隔层，以使用图案化掩模层作为蚀刻掩模在第一侧壁间隔物上限定牺牲侧壁间隔物。 然后使用牺牲侧壁间隔件作为植入物掩模，将掺杂剂的PFET晕注入物执行到邻近栅电极延伸的部分半导体衬底。 在该注入步骤之后，源极和漏极区沟槽在栅电极的相对侧被蚀刻到半导体衬底中。 然后通过在其中外延生长SiGe源极和漏极区域来填充这些源极和漏极区沟槽。

    Semiconductor fabrication process including an SiGe rework method
    4.
    发明授权
    Semiconductor fabrication process including an SiGe rework method 有权
    半导体制造工艺包括SiGe返工方法

    公开(公告)号：US07955936B2

    公开(公告)日：2011-06-07

    申请号：US12172756

    申请日：2008-07-14

    申请人： Yong Siang Tan ,  Chung Woh Lai ,  Jin-Ping Han ,  Henry K. Utomo ,  Judson R. Holt ,  Eric Harley ,  Richard O. Henry ,  Richard J. Murphy

    发明人： Yong Siang Tan ,  Chung Woh Lai ,  Jin-Ping Han ,  Henry K. Utomo ,  Judson R. Holt ,  Eric Harley ,  Richard O. Henry ,  Richard J. Murphy

    IPC分类号： H01L21/336

    CPC分类号： H01L29/1054 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

    摘要： A method for fabricating a semiconductor device includes forming an SiGe region. The SiGe region can be an embedded source and drain region, or a compressive SiGe channel layer, or other SiGe regions within a semiconductor device. The SiGe region is exposed to an SC1 solution and excess surface portions of the SiGe region are selectively removed. The SC1 etching process can be part of a rework method in which overgrowth regions of SiGe are selectively removed by exposing the SiGe to and SC1 solution maintained at an elevated temperature. The etching process is carried out for a period of time sufficient to remove excess surface portions of SiGe. The SC1 etching process can be carried out at elevated temperatures ranging from about 25° C. to about 65° C.

    摘要翻译： 一种制造半导体器件的方法包括形成SiGe区域。 SiGe区可以是嵌入式源极和漏极区域，或者是半导体器件内的压缩SiGe沟道层或其它SiGe区域。 将SiGe区域暴露于SC1溶液，并且选择性地除去SiGe区域的多余表面部分。 SC1蚀刻工艺可以是返工方法的一部分，其中通过暴露SiGe和保持在升高的温度下的SC1溶液来选择性地除去SiGe的过度生长区域。 进行蚀刻处理足以除去SiGe的多余表面部分的一段时间。 SC1蚀刻工艺可以在约25℃至约65℃的升高的温度下进行。

    Methods of Forming P-Channel Field Effect Transistors Having SiGe Source/Drain Regions
    5.
    发明申请
    Methods of Forming P-Channel Field Effect Transistors Having SiGe Source/Drain Regions 有权
    形成具有SiGe源极/漏极区域的P沟道场效应晶体管的方法

    公开(公告)号：US20110237039A1

    公开(公告)日：2011-09-29

    申请号：US12729486

    申请日：2010-03-23

    申请人： Jong-Ho Yang ,  Hyung-rae Lee ,  Jin-Ping Han ,  Chung Woh Lai ,  Henry K. Utomo ,  Thomas W. Dyer

    发明人： Jong-Ho Yang ,  Hyung-rae Lee ,  Jin-Ping Han ,  Chung Woh Lai ,  Henry K. Utomo ,  Thomas W. Dyer

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

    摘要： Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrificial sidewall spacer layer on the gate electrode. A mask layer is then patterned on the gate electrode. The sacrificial sidewall spacer layer is selectively etched to define sacrificial sidewall spacers on the first sidewall spacers, using the patterned mask layer as an etching mask. A PFET halo-implant of dopants is then performed into portions of the semiconductor substrate that extend adjacent the gate electrode, using the sacrificial sidewall spacers as an implant mask. Following this implant step, source and drain region trenches are etched into the semiconductor substrate, on opposite sides of the gate electrode. These source and drain region trenches are then filled by epitaxially growing SiGe source and drain regions therein.

    摘要翻译： 形成p沟道MOSFET的方法使用在制造过程中相对较早执行的光晕注入步骤。 这些方法包括在半导体衬底上形成其上具有第一侧壁间隔物的栅电极，然后在栅电极上形成牺牲侧壁间隔层。 然后在栅极电极上形成掩模层。 选择性地蚀刻牺牲侧壁间隔层，以使用图案化掩模层作为蚀刻掩模在第一侧壁间隔物上限定牺牲侧壁间隔物。 然后使用牺牲侧壁间隔件作为植入物掩模，将掺杂剂的PFET晕注入物执行到邻近栅电极延伸的部分半导体衬底。 在该注入步骤之后，源极和漏极区沟槽在栅电极的相对侧被蚀刻到半导体衬底中。 然后通过在其中外延生长SiGe源极和漏极区域来填充这些源极和漏极区沟槽。

    Semiconductor Fabrication Process Including An SiGe Rework Method
    6.
    发明申请
    Semiconductor Fabrication Process Including An SiGe Rework Method 有权
    包括SiGe返工方法的半导体制造工艺

    公开(公告)号：US20100009502A1

    公开(公告)日：2010-01-14

    申请号：US12172756

    申请日：2008-07-14

    申请人： Yong Siang Tan ,  Chung Woh Lai ,  Jin-Ping Han ,  Henry K. Utomo ,  Judson R. Holt ,  Eric Harley ,  Richard O. Henry ,  Richard J. Murphy

    发明人： Yong Siang Tan ,  Chung Woh Lai ,  Jin-Ping Han ,  Henry K. Utomo ,  Judson R. Holt ,  Eric Harley ,  Richard O. Henry ,  Richard J. Murphy

    IPC分类号： H01L21/336

    CPC分类号： H01L29/1054 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

    摘要： A method for fabricating a semiconductor device includes forming an SiGe region. The SiGe region can be an embedded source and drain region, or a compressive SiGe channel layer, or other SiGe regions within a semiconductor device. The SiGe region is exposed to an SC1 solution and excess surface portions of the SiGe region are selectively removed. The SC1 etching process can be part of a rework method in which overgrowth regions of SiGe are selectively removed by exposing the SiGe to and SC1 solution maintained at an elevated temperature. The etching process is carried out for a period of time sufficient to remove excess surface portions of SiGe. The SC1 etching process can be carried out at elevated temperatures ranging from about 25° C. to about 65° C.

    摘要翻译： 一种制造半导体器件的方法包括形成SiGe区域。 SiGe区可以是嵌入式源极和漏极区域，或者是半导体器件内的压缩SiGe沟道层或其它SiGe区域。 将SiGe区域暴露于SC1溶液，并且选择性地除去SiGe区域的多余表面部分。 SC1蚀刻工艺可以是返工方法的一部分，其中通过暴露SiGe和保持在升高的温度下的SC1溶液来选择性地除去SiGe的过度生长区域。 进行蚀刻处理足以除去SiGe的多余表面部分的一段时间。 SC1蚀刻工艺可以在约25℃至约65℃的升高的温度下进行。

    Strained semiconductor device and method of making same
    7.
    发明申请
    Strained semiconductor device and method of making same 有权
    应变半导体器件及其制造方法

    公开(公告)号：US20070295989A1

    公开(公告)日：2007-12-27

    申请号：US11473883

    申请日：2006-06-23

    申请人： Jin-Ping Han ,  Hung Y. Ng ,  Judson R. Holt

    发明人： Jin-Ping Han ,  Hung Y. Ng ,  Judson R. Holt

    IPC分类号： H01L31/00 ,  H01L21/336

    CPC分类号： H01L29/78 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

    摘要： A semiconductor body is formed from a first semiconductor material, e.g., silicon. A compound semiconductor region, e.g., silicon germanium, is embedded in the semiconductor body. The compound semiconductor region includes the first semiconductor material and a second semiconductor material. The compound semiconductor region has a concentration of the second semiconductor material that varies along an interface between the side portion of the compound semiconductor region and the side portion of the semiconductor body

    摘要翻译： 半导体本体由诸如硅的第一半导体材料形成。 诸如硅锗的化合物半导体区域被嵌入在半导体本体中。 化合物半导体区域包括第一半导体材料和第二半导体材料。 化合物半导体区域具有沿着化合物半导体区域的侧部与半导体本体的侧部之间的界面变化的第二半导体材料的浓度

    Strained semiconductor device and method of making same
    8.
    发明授权
    Strained semiconductor device and method of making same 有权
    应变半导体器件及其制造方法

    公开(公告)号：US07772676B2

    公开(公告)日：2010-08-10

    申请号：US11473883

    申请日：2006-06-23

    申请人： Jin-Ping Han ,  Hung Y. Ng ,  Judson R. Holt

    发明人： Jin-Ping Han ,  Hung Y. Ng ,  Judson R. Holt

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/78 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

    摘要： A semiconductor body is formed from a first semiconductor material, e.g., silicon. A compound semiconductor region, e.g., silicon germanium, is embedded in the semiconductor body. The compound semiconductor region includes the first semiconductor material and a second semiconductor material. The compound semiconductor region has a concentration of the second semiconductor material that varies along an interface between the side portion of the compound semiconductor region and the side portion of the semiconductor body

    摘要翻译： 半导体本体由诸如硅的第一半导体材料形成。 诸如硅锗的化合物半导体区域被嵌入在半导体本体中。 化合物半导体区域包括第一半导体材料和第二半导体材料。 化合物半导体区域具有沿着化合物半导体区域的侧部与半导体本体的侧部之间的界面变化的第二半导体材料的浓度

    Semiconductor devices and methods of manufacture thereof
    10.
    发明授权
    Semiconductor devices and methods of manufacture thereof 有权
    半导体器件及其制造方法

    公开(公告)号：US09209088B2

    公开(公告)日：2015-12-08

    申请号：US11832449

    申请日：2007-08-01

    申请人： Manfred Eller ,  Jin-Ping Han

    发明人： Manfred Eller ,  Jin-Ping Han

    IPC分类号： H01L21/3205 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66

    CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843

    摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a gate dielectric over the semiconductor wafer, and forming a gate over the gate dielectric. At least one recess is formed in the semiconductor wafer proximate the gate and the gate dielectric, at least a portion of the at least one recess extending beneath the gate. The at least one recess in the semiconductor wafer is filled with a semiconductive material.

    摘要翻译： 公开了半导体器件及其制造方法。 在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片上形成栅极电介质，并在栅极电介质上形成栅极。 至少一个凹部形成在靠近栅极和栅极电介质的半导体晶片中，至少一个凹部的至少一部分在栅极下方延伸。 半导体晶片中的至少一个凹部填充有半导体材料。