公开(公告)号：US20110175148A1

公开(公告)日：2011-07-21

申请号：US13074888

申请日：2011-03-29

Applicant: Jiang Yan ,  Roland Hampp ,  Jin-Ping Han ,  Manfred Eller ,  Alois Gutmann

Inventor： Jiang Yan ,  Roland Hampp ,  Jin-Ping Han ,  Manfred Eller ,  Alois Gutmann

IPC: H01L29/772

CPC classification number: H01L21/76804 ,  H01L21/823807 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming features and structures thereof are disclosed. In one embodiment, a method of forming a feature includes forming a first material over a workpiece, forming a first pattern for a lower portion of the feature in the first material, and filling the first pattern with a sacrificial material. A second material is formed over the first material and the sacrificial material, and a second pattern for an upper portion of the feature is formed in the second material. The sacrificial material is removed. The first pattern and the second pattern are filled with a third material.

Abstract translation: 公开了形成特征及其结构的方法。 在一个实施例中，形成特征的方法包括在工件上形成第一材料，形成用于第一材料中特征的下部的第一图案，以及用牺牲材料填充第一图案。 在第一材料和牺牲材料上形成第二材料，并且在第二材料中形成用于特征的上部的第二图案。 牺牲材料被去除。 第一图案和第二图案填充有第三材料。

公开(公告)号：US20090227086A1

公开(公告)日：2009-09-10

申请号：US12043384

申请日：2008-03-06

Applicant: Roland Hampp ,  Manfred Eller ,  Jin-Ping Han ,  Matthias Lipinski

Inventor： Roland Hampp ,  Manfred Eller ,  Jin-Ping Han ,  Matthias Lipinski

IPC: H01L21/76

CPC classification number: H01L21/76262 ,  H01L21/76278

Abstract: The prevention of active area loss in the STI model is disclosed which results in an improved device performance in devices manufactured according to the process flow. The process generally shared among the multiple various embodiments inverts the current conventional STI structure towards a process flow where an insulator is patterned with tapered trenches. A segregation layer is formed beneath the surface of the insulator in the tapered trenches. The tapered trenches are then filled with a semiconductor material which is further processed to create a number of active devices. Therefore, the active devices are created in patterned dielectric instead of the STI being created in the semiconductor substrate of the active devices.

Abstract translation: 公开了STI模型中的有源面积损耗的防止，这导致根据工艺流程制造的器件中的器件性能提高。 多个不同实施例中通常共享的方法将当前常规STI结构转换为绝缘体用锥形图案化的工艺流程。 在锥形沟槽中的绝缘体的表面下方形成偏析层。 然后用半导体材料填充锥形沟槽，半导体材料被进一步处理以产生多个有源器件。 因此，有源器件是在图案化电介质中产生的，而不是在有源器件的半导体衬底中产生的STI。

公开(公告)号：US20090032841A1

公开(公告)日：2009-02-05

申请号：US11832449

申请日：2007-08-01

Applicant: Manfred Eller ,  Jin-Ping Han

Inventor： Manfred Eller ,  Jin-Ping Han

IPC: H01L29/778 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a gate dielectric over the semiconductor wafer, and forming a gate over the gate dielectric. At least one recess is formed in the semiconductor wafer proximate the gate and the gate dielectric, at least a portion of the at least one recess extending beneath the gate. The at least one recess in the semiconductor wafer is filled with a semiconductive material.

Abstract translation: 公开了半导体器件及其制造方法。 在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片上形成栅极电介质，并在栅极电介质上形成栅极。 至少一个凹部形成在靠近栅极和栅极电介质的半导体晶片中，至少一个凹部的至少一部分在栅极下方延伸。 半导体晶片中的至少一个凹部填充有半导体材料。

公开(公告)号：US20080076214A1

公开(公告)日：2008-03-27

申请号：US11526499

申请日：2006-09-25

Applicant: Jin-Ping Han ,  Haoren Zhuang ,  Jiang Yan ,  Jingyu Lian ,  Manfred Eller

Inventor： Jin-Ping Han ,  Haoren Zhuang ,  Jiang Yan ,  Jingyu Lian ,  Manfred Eller

IPC: H01L21/8234 ,  H01L21/336

CPC classification number: H01L29/4983 ,  H01L21/28017 ,  H01L21/28123 ,  H01L21/28194 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/82385 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78

Abstract: A method of making a semiconductor device is disclosed. A device is fabricated on a semiconductor body. A gate electrode is disposed over the semiconductor body with a gate dielectric between the gate electrode and the semiconductor body, wherein the gate dielectric has a length greater than the gate electrode. A first source/drain region is disposed within the semiconductor body adjacent to the first edge of the gate with the gate dielectric at least partially overlapping the first source/drain region, and a second source/drain region is disposed within the semiconductor body adjacent to the first edge of the gate with the gate dielectric at least partially overlapping the second source/drain region.

Abstract translation: 公开了制造半导体器件的方法。 器件制造在半导体主体上。 栅电极设置在半导体本体上，在栅电极和半导体本体之间具有栅极电介质，其中栅极电介质具有大于栅电极的长度。 第一源极/漏极区域设置在与栅极的第一边缘相邻的半导体本体内，栅极电介质至少部分地与第一源极/漏极区域重叠，并且第二源极/漏极区域设置在与半导体本体相邻的第二源极/漏极区域内 具有栅极电介质的栅极的第一边缘至少部分地与第二源极/漏极区重叠。

公开(公告)号：US09209088B2

公开(公告)日：2015-12-08

申请号：US11832449

申请日：2007-08-01

Applicant: Manfred Eller ,  Jin-Ping Han

Inventor： Manfred Eller ,  Jin-Ping Han

IPC: H01L21/3205 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a gate dielectric over the semiconductor wafer, and forming a gate over the gate dielectric. At least one recess is formed in the semiconductor wafer proximate the gate and the gate dielectric, at least a portion of the at least one recess extending beneath the gate. The at least one recess in the semiconductor wafer is filled with a semiconductive material.

Abstract translation: 公开了半导体器件及其制造方法。 在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片上形成栅极电介质，并在栅极电介质上形成栅极。 至少一个凹部形成在靠近栅极和栅极电介质的半导体晶片中，至少一个凹部的至少一部分在栅极下方延伸。 半导体晶片中的至少一个凹部填充有半导体材料。

公开(公告)号：US09070759B2

公开(公告)日：2015-06-30

申请号：US11526499

申请日：2006-09-25

Applicant: Jin-Ping Han ,  Haoren Zhuang ,  Jiang Yan ,  Jingyu Lian ,  Manfred Eller

Inventor： Jin-Ping Han ,  Haoren Zhuang ,  Jiang Yan ,  Jingyu Lian ,  Manfred Eller

IPC: H01L21/336 ,  H01L21/311 ,  H01L29/51 ,  H01L29/78 ,  H01L29/423 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/4983 ,  H01L21/28017 ,  H01L21/28123 ,  H01L21/28194 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/82385 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78

Abstract: A method of making a semiconductor device is disclosed. A device is fabricated on a semiconductor body. A gate electrode is disposed over the semiconductor body with a gate dielectric between the gate electrode and the semiconductor body, wherein the gate dielectric has a length greater than the gate electrode. A first source/drain region is disposed within the semiconductor body adjacent to the first edge of the gate with the gate dielectric at least partially overlapping the first source/drain region, and a second source/drain region is disposed within the semiconductor body adjacent to the first edge of the gate with the gate dielectric at least partially overlapping the second source/drain region.

Abstract translation: 公开了制造半导体器件的方法。 器件制造在半导体主体上。 栅电极设置在半导体本体上，在栅电极和半导体本体之间具有栅极电介质，其中栅极电介质具有大于栅电极的长度。 第一源极/漏极区域设置在与栅极的第一边缘相邻的半导体本体内，栅极电介质至少部分地与第一源极/漏极区域重叠，并且第二源极/漏极区域设置在与半导体本体相邻的第二源极/漏极区域内 具有栅极电介质的栅极的第一边缘至少部分地与第二源极/漏极区重叠。

公开(公告)号：US07947606B2

公开(公告)日：2011-05-24

申请号：US12129479

申请日：2008-05-29

Applicant: Jiang Yan ,  Roland Hampp ,  Jin-Ping Han ,  Manfred Eller ,  Alois Gutmann

Inventor： Jiang Yan ,  Roland Hampp ,  Jin-Ping Han ,  Manfred Eller ,  Alois Gutmann

IPC: H01L21/311

CPC classification number: H01L21/76804 ,  H01L21/823807 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming features and structures thereof are disclosed. In one embodiment, a method of forming a feature includes forming a first material over a workpiece, forming a first pattern for a lower portion of the feature in the first material, and filling the first pattern with a sacrificial material. A second material is formed over the first material and the sacrificial material, and a second pattern for an upper portion of the feature is formed in the second material. The sacrificial material is removed. The first pattern and the second pattern are filled with a third material.

Abstract translation: 公开了形成特征及其结构的方法。 在一个实施例中，形成特征的方法包括在工件上形成第一材料，形成用于第一材料中特征的下部的第一图案，以及用牺牲材料填充第一图案。 在第一材料和牺牲材料上形成第二材料，并且在第二材料中形成用于特征的上部的第二图案。 牺牲材料被去除。 第一图案和第二图案填充有第三材料。

公开(公告)号：US20090294986A1

公开(公告)日：2009-12-03

申请号：US12129479

申请日：2008-05-29

Applicant: Jiang Yan ,  Roland Hampp ,  Jin-Ping Han ,  Manfred Eller ,  Alois Gutmann

Inventor： Jiang Yan ,  Roland Hampp ,  Jin-Ping Han ,  Manfred Eller ,  Alois Gutmann

IPC: H01L23/52 ,  H01L21/4763 ,  H01L21/8238

CPC classification number: H01L21/76804 ,  H01L21/823807 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming features and structures thereof are disclosed. In one embodiment, a method of forming a feature includes forming a first material over a workpiece, forming a first pattern for a lower portion of the feature in the first material, and filling the first pattern with a sacrificial material. A second material is formed over the first material and the sacrificial material, and a second pattern for an upper portion of the feature is formed in the second material. The sacrificial material is removed. The first pattern and the second pattern are filled with a third material.

Abstract translation: 公开了形成特征及其结构的方法。 在一个实施例中，形成特征的方法包括在工件上形成第一材料，形成用于第一材料中特征的下部的第一图案，以及用牺牲材料填充第一图案。 在第一材料和牺牲材料上形成第二材料，并且在第二材料中形成用于特征的上部的第二图案。 牺牲材料被去除。 第一图案和第二图案填充有第三材料。

公开(公告)号：US07892939B2

公开(公告)日：2011-02-22

申请号：US12043384

申请日：2008-03-06

Applicant: Roland Hampp ,  Manfred Eller ,  Jin-Ping Han ,  Matthias Lipinski

Inventor： Roland Hampp ,  Manfred Eller ,  Jin-Ping Han ,  Matthias Lipinski

IPC: H01L21/76 ,  H01L21/311

CPC classification number: H01L21/76262 ,  H01L21/76278

Abstract: The prevention of active area loss in the STI model is disclosed which results in an improved device performance in devices manufactured according to the process flow. The process generally shared among the multiple various embodiments inverts the current conventional STI structure towards a process flow where an insulator is patterned with tapered trenches. A segregation layer is formed beneath the surface of the insulator in the tapered trenches. The tapered trenches are then filled with a semiconductor material which is further processed to create a number of active devices. Therefore, the active devices are created in patterned dielectric instead of the STI being created in the semiconductor substrate of the active devices.

Abstract translation: 公开了STI模型中的有源面积损耗的防止，这导致根据工艺流程制造的器件中的器件性能提高。 多个不同实施例中通常共享的方法将当前常规STI结构转换为绝缘体用锥形图案化的工艺流程。 在锥形沟槽中的绝缘体的表面下方形成偏析层。 然后用半导体材料填充锥形沟槽，半导体材料被进一步处理以产生多个有源器件。 因此，有源器件是在图案化电介质中产生的，而不是在有源器件的半导体衬底中产生的STI。

公开(公告)号：US07820518B2

公开(公告)日：2010-10-26

申请号：US12129510

申请日：2008-05-29

Applicant: Manfred Eller ,  Jiang Yan ,  Jin-Ping Han ,  Alois Gutmann

Inventor： Manfred Eller ,  Jiang Yan ,  Jin-Ping Han ,  Alois Gutmann

IPC: H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

Abstract: Methods of fabricating transistors and semiconductor devices and structures thereof are disclosed. In one embodiment, a method of fabricating a transistor includes forming a gate dielectric over a workpiece, forming a gate over the gate dielectric, and forming a stress-inducing material over the gate, the gate dielectric, and the workpiece. Sidewall spacers are formed from the stress-inducing material on sidewalls of the gate and the gate dielectric.

Abstract translation: 公开了制造晶体管和半导体器件的方法及其结构。 在一个实施例中，制造晶体管的方法包括在工件上形成栅极电介质，在栅极电介质上形成栅极，并在栅极，栅极电介质和工件上形成应力诱发材料。 侧壁间隔物由栅极和栅极电介质的侧壁上的应力诱导材料形成。