公开(公告)号：US20250107095A1

公开(公告)日：2025-03-27

申请号：US18976999

申请日：2024-12-11

Applicant: Kioxia Corporation

Inventor： Tadashi IGUCHI ,  Murato KAWAI ,  Toru MATSUDA ,  Hisashi KATO ,  Megumi ISHIDUKI

IPC: H10B43/27 ,  G11C16/04 ,  H01L21/764 ,  H01L23/522 ,  H01L29/792 ,  H10B41/20 ,  H10B41/27 ,  H10B43/10 ,  H10B43/20 ,  H10B43/50

Abstract: A method of producing a semiconductor memory device includes, when three directions crossing each other are set to first, second, and third directions, respectively, laminating a plurality of first laminates and a plurality of second laminates on a semiconductor substrate in the third direction. The method further includes forming ends of the plurality of first laminates in shapes of steps extending in the first direction, and forming ends of the plurality of second laminates in shapes of steps extending in both directions of the first direction and the second direction.

公开(公告)号：US20250031367A1

公开(公告)日：2025-01-23

申请号：US18905560

申请日：2024-10-03

Applicant: KIOXIA CORPORATION

Inventor： Takuya INATSUKA ,  Tadashi IGUCHI ,  Murato KAWAI ,  Hisashi KATO ,  Megumi ISHIDUKI

IPC: H10B43/10 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/50 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.

公开(公告)号：US20240297146A1

公开(公告)日：2024-09-05

申请号：US18589254

申请日：2024-02-27

Applicant: Kioxia Corporation

Inventor： Shota KONUMA ,  Hiroshi FUJITA ,  Hisashi KATO ,  Naomi YANAI

IPC: H01L23/00 ,  H01L21/265 ,  H01L21/324 ,  H10B80/00

CPC classification number: H01L24/96 ,  H01L21/2652 ,  H01L21/324 ,  H10B80/00 ,  H01L2224/96

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming, on a substrate, an active layer in which a dopant is implanted; forming a porous layer by making the active layer porous by an anodization treatment; forming a device layer including at least a part of a configuration of the semiconductor device above the porous layer; and cleaving the porous layer to remove the substrate.

公开(公告)号：US20220173032A1

公开(公告)日：2022-06-02

申请号：US17667955

申请日：2022-02-09

Applicant: KIOXIA CORPORATION

Inventor： Hisashi KATO

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/1157

Abstract: According to one embodiment, a semiconductor memory device includes first and second conductor layers, a first pillar, a first contact, and a source line drive circuit. The first pillar is passing through the second conductor layers. The first pillar includes a first semiconductor layer and a second insulator layer. The first semiconductor layer includes a side surface partially in contact with the first conductor layer. The first contact is passing through the second conductor layers. The first contact includes a third conductor layer and a third insulator layer. The third conductor layer includes a side surface partially in contact with the first conductor layer. The source line drive circuit is electrically coupled to the first conductor layer via the first contact.

公开(公告)号：US20250096115A1

公开(公告)日：2025-03-20

申请号：US18961802

申请日：2024-11-27

Applicant: KIOXIA CORPORATION

Inventor： Hisashi KATO

IPC: H01L23/522 ,  H01L23/528 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a semiconductor memory device includes first and second conductor layers, a first pillar, a first contact, and a source line drive circuit. The first pillar is passing through the second conductor layers. The first pillar includes a first semiconductor layer and a second insulator layer. The first semiconductor layer includes a side surface partially in contact with the first conductor layer. The first contact is passing through the second conductor layers. The first contact includes a third conductor layer and a third insulator layer. The third conductor layer includes a side surface partially in contact with the first conductor layer. The source line drive circuit is electrically coupled to the first conductor layer via the first contact.

公开(公告)号：US20250029956A1

公开(公告)日：2025-01-23

申请号：US18777303

申请日：2024-07-18

Applicant: Kioxia Corporation

Inventor： Yasunori IWASHITA ,  Hisashi KATO ,  Hiroaki ASHIDATE ,  Masayoshi TAGAMI

IPC: H01L25/065 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor memory device includes first and second chips that are bonded together. The first chip includes a stacked body in which memory cells are formed and first bonding electrodes, and the second chip includes second bonding electrodes. The first bonding electrodes and the second bonding electrodes are joined to each other to form joining electrodes. The stacked body includes an insulating layer that extends in a first direction to separate the stacked body in a second direction. The joining electrodes include first and second joining electrodes, the first joining electrodes being disposed adjacent to a first side of the insulating layer in a third direction, and the second joining electrodes being disposed adjacent to a second side of the insulating layer in the third direction. The first joining electrodes and the second joining electrodes are disposed in a staggered arrangement in the second direction and the third direction.

公开(公告)号：US20230395499A1

公开(公告)日：2023-12-07

申请号：US18180442

申请日：2023-03-08

Applicant: Kioxia Corporation

Inventor： Hiroaki ASHIDATE ,  Hisashi KATO ,  Tomoyuki TAKEISHI

IPC: H01L23/528 ,  H01L23/522 ,  H10B41/20 ,  H10B43/20

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H10B41/20 ,  H10B43/20

Abstract: In one embodiment, a semiconductor device includes a first substrate, a first insulator provided on the first substrate, a first pad provided in the first insulator, a second insulator provided on the first insulator, and a second pad provided in the second insulator, disposed on the first pad, and being in contact with the first pad. The device further includes a third pad provided in the second insulator, and disposed above the second pad, a third insulator provided on the second insulator, and a fourth pad provided in the third insulator, disposed on the third pad, and being in contact with the third pad. Furthermore, a shape of the third or fourth pad is different from a shape of the first or second pad.

公开(公告)号：US20220262744A1

公开(公告)日：2022-08-18

申请号：US17411238

申请日：2021-08-25

Applicant: Kioxia Corporation

Inventor： Mitsunori MASAKI ,  Hisashi KATO ,  Kazuhiro NOJIMA ,  Shoichi MIYAZAKI ,  Akira YOTSUMOTO ,  Kanako SHIGA ,  Yu HIROTSU ,  Osamu MATSUURA

IPC: H01L23/00 ,  H01L27/11556 ,  H01L27/11582

Abstract: Semiconductor memory device includes: a first and second member each extending in a first direction in a boundary part between a first and second block region and arranged in the first direction; a support pillar arranged between the first and second member at the boundary part; conductive layers separated from one another and arranged in a third direction and split by the first and second member, and the support pillar into a first and second portion; and a memory pillar penetrating through the conductive layers. The support pillar includes a lower and upper pillar. A side face of the lower pillar and an extension of a side face of the upper pillar are displaced from each other in a plane based on a second and the third direction.

公开(公告)号：US20250070023A1

公开(公告)日：2025-02-27

申请号：US18808257

申请日：2024-08-19

Applicant: Kioxia Corporation

Inventor： Hisashi KATO ,  Masayoshi TAGAMI ,  Akira NAKAJIMA

IPC: H01L23/528 ,  G11C16/04 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: A semiconductor device includes a first chip including a first insulating layer; a second chip bonded to the first chip and including a second insulating layer; and a pad provided around a bonded surface between the first chip and the second chip. The pad includes a first metal layer including a first metal, a second metal layer disposed between the first metal layer and the first insulating layer, and a third metal layer disposed between the first metal layer and the second insulating layer. At least one of the second metal layer or the third metal layer include a second metal having oxidation energy lower than oxidation energy of the first metal. The first metal layer further includes the second metal.

公开(公告)号：US20230397445A1

公开(公告)日：2023-12-07

申请号：US18175873

申请日：2023-02-28

Applicant: Kioxia Corporation

Inventor： Hisashi KATO

IPC: H10B80/00

CPC classification number: H10B80/00

Abstract: A semiconductor memory device includes a first chip, a second chip, a third chip, and a fourth chip. The second chip is bonded to the first chip. The third chip is bonded to the second chip on a side opposite to the first chip. The fourth chip is bonded to the third chip on a side opposite to the second chip. The third chip includes a first stacked body in which a plurality of first conductive layers are stacked in a first direction. The second chip includes a second stacked body in which a plurality of second conductive layers are stacked in the first direction. The first and second conductive layers each longitudinally extend in a second direction perpendicular to the first direction. The fourth chip includes a plurality of line patterns each extending in the second direction and aligned with each other in a third direction.