公开(公告)号：US20230088929A1

公开(公告)日：2023-03-23

申请号：US17892940

申请日：2022-08-22

Applicant: Kioxia Corporation

Inventor： Natsuki FUKUDA ,  Tadashi IGUCHI

IPC: H01L27/11582 ,  H01L27/11556

Abstract: A semiconductor memory device includes a substrate including a first region and a second region, a plurality of first conductive layers, a first semiconductor layer disposed in the first region, an electric charge accumulating layer, a contact electrode disposed in the second region and connected to one of the plurality of first conductive layers, and a plurality of first structures and a plurality of second structures disposed in the second region. The first structure includes a second semiconductor layer opposed to the plurality of first conductive layers and including a semiconductor material in common with the first semiconductor layer, and a first insulating layer disposed between the plurality of first conductive layers and the second semiconductor layer and including an insulating material in common with the electric charge accumulating layer. The second structure does not include the semiconductor material or the insulating material.

公开(公告)号：US20240121962A1

公开(公告)日：2024-04-11

申请号：US18461326

申请日：2023-09-05

Applicant: Kioxia Corporation

Inventor： Satoshi NAGASHIMA ,  Shota KASHIYAMA ,  Tadashi IGUCHI ,  Takuya NISHIKAWA

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: According to one embodiment, a semiconductor device includes a stacked film with first insulating films and electrode layers alternately stacked in a first direction. The device further includes a columnar portion extending in the first direction and provided in a first region of the stacked film. The columnar portion forms memory cells at its intersections with the electrode layers. The device further includes a support column portion provided in a second region and extending in the first direction. A conductive plug is provided on a first electrode layer among the electrode layers in the second region. A first side surface of the support column portion faces a second side surface of the plug and the second side surface is concave in a direction toward the first side surface.

公开(公告)号：US20230326859A1

公开(公告)日：2023-10-12

申请号：US17940158

申请日：2022-09-08

Applicant: Kioxia Corporation

Inventor： Natsuki FUKUDA ,  Tadashi IGUCHI

IPC: H01L27/11582 ,  H01L23/535

CPC classification number: H01L23/535 ,  H01L27/11582

Abstract: Contact plugs extend along a first axis. Each contact plug includes a second conductor and a first insulator. A first insulator is between the first conductors and the second conductor. A lower face of each contact plug is in contact with an upper face of a unique one of the first conductors. A first one and second one of the contact plugs are adjacent along a second axis that crosses the first axis. A third one of the contact plugs is between the first and second contact plugs on the second axis, and is at a different position from positions of the first and second contact plugs on a third axis orthogonal to the first and second axes.

公开(公告)号：US20250031367A1

公开(公告)日：2025-01-23

申请号：US18905560

申请日：2024-10-03

Applicant: KIOXIA CORPORATION

Inventor： Takuya INATSUKA ,  Tadashi IGUCHI ,  Murato KAWAI ,  Hisashi KATO ,  Megumi ISHIDUKI

IPC: H10B43/10 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/50 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.

公开(公告)号：US20240099001A1

公开(公告)日：2024-03-21

申请号：US18460506

申请日：2023-09-01

Applicant: Kioxia Corporation

Inventor： Tadashi IGUCHI

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: According to one embodiment, a semiconductor memory device has a first film and a stacked body on the first film. The stacked body includes insulating films and conductive films stacked in a first direction. A first pillar extends through the stacked body and has a first semiconductor portion and a first insulator portion on an outer peripheral surface. A plurality of second pillars extend in the stacked body and reach the first film. The second pillars each comprise an insulator material and have a bottom surface with a protrusion protruding into the first film. A third pillar extends in the stacked body between adjacent second pillars. The third pillar comprises a conductor material that is electrically connected to one of the conductive films of the stacked body.

公开(公告)号：US20230090305A1

公开(公告)日：2023-03-23

申请号：US17686209

申请日：2022-03-03

Applicant: Kioxia Corporation

Inventor： Tadashi IGUCHI ,  Natsuki FUKUDA

IPC: H01L23/535 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor storage device includes a substrate having a memory region and a hook-up region arranged in a first direction and a plurality of memory structures arranged in a second direction intersecting the first direction. The plurality of memory structures include a plurality of conductive layers arranged in a third direction intersecting a surface of the substrate and extending in the first direction over the memory region and the hook-up region and a plurality of contact electrodes provided in the hook-up region and extending in the third direction to have an outer peripheral surface surrounded by a part of the plurality of conductive layers, each contact electrode being connected to any of the plurality of conductive layers. The hook-up region includes a first area and a second area arranged in the first direction. The first region includes a first contact electrode and a second contact electrode, and the second region includes a third contact electrode. A length of the third contact electrode in the third direction is larger than a length of the first contact electrode in the third direction, and is smaller than a length of the second contact electrode in the third direction.

公开(公告)号：US20220285389A1

公开(公告)日：2022-09-08

申请号：US17397165

申请日：2021-08-09

Applicant: Kioxia Corporation

Inventor： Natsuki FUKUDA ,  Tadashi IGUCHI

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11521

Abstract: A semiconductor memory device includes a substrate, conductive layers arranged in a first direction and extend in a second direction, a semiconductor layer extending in the first direction and opposed to the conductive layers, and n contact electrode regions arranged in a third direction. The n is a power of 2. The contact electrode region includes contact electrodes arranged in the second direction. The conductive layers include a first conductive layer and a second conductive layer that is an n-th conductive layer counted from the first conductive layer. The contact electrodes include a first contact electrode connected to the first conductive layer, a second contact electrode connected to the second conductive layer, and a third contact electrode disposed between them. The first contact electrode, the second contact electrode, and the third contact electrode are arranged in the second direction or the third direction.

公开(公告)号：US20210280600A1

公开(公告)日：2021-09-09

申请号：US17010454

申请日：2020-09-02

Applicant: Kioxia Corporation

Inventor： Tadashi IGUCHI

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/522

Abstract: A semiconductor storage device includes: a substrate having a front surface; a plurality of conductive layers arranged in a first direction, the first direction intersecting the front surface of the substrate; a plurality of memory cells connected to the plurality of conductive layers; a contact electrode extending in the first direction and connected to one of the plurality of conductive layers; and an insulating structure extending in the first direction, the insulating structure connected to an end portion of the contact electrode on one side of the contact electrode in the first direction, and penetrating the plurality of conductive layers.

公开(公告)号：US20250107095A1

公开(公告)日：2025-03-27

申请号：US18976999

申请日：2024-12-11

Applicant: Kioxia Corporation

Inventor： Tadashi IGUCHI ,  Murato KAWAI ,  Toru MATSUDA ,  Hisashi KATO ,  Megumi ISHIDUKI

IPC: H10B43/27 ,  G11C16/04 ,  H01L21/764 ,  H01L23/522 ,  H01L29/792 ,  H10B41/20 ,  H10B41/27 ,  H10B43/10 ,  H10B43/20 ,  H10B43/50

Abstract: A method of producing a semiconductor memory device includes, when three directions crossing each other are set to first, second, and third directions, respectively, laminating a plurality of first laminates and a plurality of second laminates on a semiconductor substrate in the third direction. The method further includes forming ends of the plurality of first laminates in shapes of steps extending in the first direction, and forming ends of the plurality of second laminates in shapes of steps extending in both directions of the first direction and the second direction.

公开(公告)号：US20240292626A1

公开(公告)日：2024-08-29

申请号：US18585206

申请日：2024-02-23

Applicant: Kioxia Corporation

Inventor： Kazuki SHOJI ,  Tadashi IGUCHI

IPC: H10B43/35 ,  H10B43/10 ,  H10B43/20

CPC classification number: H10B43/35 ,  H10B43/10 ,  H10B43/20

Abstract: A semiconductor memory device includes a first stacked body that includes first insulating films and first conductive films alternately stacked in a first direction; first columnar bodies each including a first semiconductor structure extending through the first stacked body, the plurality of first columnar bodies being configured as memory cells; and a plurality of second columnar bodies that each include at least one conductor extending through the first stacked body in the first direction, and are each coupled to a corresponding one of the first conductive films and a stacked film including second, third, and fourth insulating films, wherein the second to fourth insulating films are provided between the at least one conductor and the first stacked body.