公开(公告)号：US11704152B2

公开(公告)日：2023-07-18

申请号：US17232332

申请日：2021-04-16

Applicant: Kioxia Corporation

Inventor： Julien Margetts

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4881 ,  G06F9/5038

Abstract: A method for scheduling tasks on a processor includes detecting, in a task selection device communicatively coupled to the processor, a condition of each of a plurality of components of a computer system comprising the processor, determining a plurality of tasks that can be next executed on the processor based on the condition of each of the plurality of components, transmitting a signal to an arbiter of the task selection device that the plurality of tasks can be executed, determining, at the arbiter, a next task to be executed on the processor, storing, by the task selection device, the entry point address of the next task to be executed on the processor, and transferring, by the processor, execution to the stored entry point address of the next task to be executed.

公开(公告)号：US20210303199A1

公开(公告)日：2021-09-30

申请号：US16836112

申请日：2020-03-31

Applicant: Kioxia Corporation

Inventor： Nigel Horspool ,  Julien Margetts

IPC: G06F3/06 ,  G06F15/78

Abstract: A solid-state drive having an integrated circuit comprising a controller that is configured to determine, for data transferred between a host interface of the integrated circuit and nonvolatile semiconductor storage device interface of the integrated circuit, the availability of an internal buffer of the integrated circuit to transparently accumulate the transferred data, and (i) if the internal buffer is available, accumulate the data from target nonvolatile semiconductor storage devices or the host in the internal buffer, or (ii) if the internal buffer is not available, accumulate the data unit from the target nonvolatile semiconductor storage devices or the host in an external buffer communicatively coupled to the controller, wherein the external buffer is external to the integrated circuit. The controller then provides the accumulated data to the respective interfaces to furnish a read or write request from the host.

公开(公告)号：US12118235B2

公开(公告)日：2024-10-15

申请号：US17402192

申请日：2021-08-13

Applicant: Kioxia Corporation

Inventor： Paul Hanham ,  Julien Margetts ,  Matthew Stephens

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0679

Abstract: Example implementations include a non-transitory processor-readable media comprising processor-readable instructions that when executed by at least one processor of a controller, causes the processor to generate at least one memory address corresponding respectively to at least one command block, the command block being associated with a command to a memory device, allocate the memory address to a buffer addressing unit associated with a host interface, the memory address including a buffer memory identifier associated with a buffer memory block and a buffer memory address associated with the buffer memory block, and update a request count associated with the buffer memory block by incrementing a reference counter associated with the buffer memory block.

公开(公告)号：US20230333774A1

公开(公告)日：2023-10-19

申请号：US18215726

申请日：2023-06-28

Applicant: Kioxia Corporation

Inventor： Nigel Horspool ,  Julien Margetts

IPC: G06F3/06 ,  G06F15/78

CPC classification number: G06F3/0656 ,  G06F3/0659 ,  G06F15/7807 ,  G06F3/0679 ,  G06F3/0614

Abstract: A solid-state drive having an integrated circuit comprising a controller that is configured to determine, for data transferred between a host interface of the integrated circuit and nonvolatile semiconductor storage device interface of the integrated circuit, the availability of an internal buffer of the integrated circuit to transparently accumulate the transferred data, and (i) if the internal buffer is available, accumulate the data from target nonvolatile semiconductor storage devices or the host in the internal buffer, or (ii) if the internal buffer is not available, accumulate the data unit from the target nonvolatile semiconductor storage devices or the host in an external buffer communicatively coupled to the controller, wherein the external buffer is external to the integrated circuit. The controller then provides the accumulated data to the respective interfaces to furnish a read or write request from the host.

公开(公告)号：US11727998B2

公开(公告)日：2023-08-15

申请号：US17512394

申请日：2021-10-27

Applicant: KIOXIA CORPORATION

Inventor： Shigehiro Asano ,  Neil Buxton ,  Julien Margetts ,  Shunichi Igahara ,  Takehiko Amaki

IPC: G11C16/26 ,  G11C16/34 ,  G11C8/12 ,  G11C16/04

CPC classification number: G11C16/3431 ,  G11C8/12 ,  G11C16/26 ,  G11C16/3495 ,  G11C16/0483

Abstract: A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.

公开(公告)号：US20230047029A1

公开(公告)日：2023-02-16

申请号：US17402192

申请日：2021-08-13

Applicant: Kioxia Corporation

Inventor： Paul Hanham ,  Julien Margetts ,  Matthew Stephens

IPC: G06F3/06

Abstract: Example implementations include a non-transitory processor-readable media comprising processor-readable instructions that when executed by at least one processor of a controller, causes the processor to generate at least one memory address corresponding respectively to at least one command block, the command block being associated with a command to a memory device, allocate the memory address to a buffer addressing unit associated with a host interface, the memory address including a buffer memory identifier associated with a buffer memory block and a buffer memory address associated with the buffer memory block, and update a request count associated with the buffer memory block by incrementing a reference counter associated with the buffer memory block.

公开(公告)号：US11726704B2

公开(公告)日：2023-08-15

申请号：US16836112

申请日：2020-03-31

Applicant: Kioxia Corporation

Inventor： Nigel Horspool ,  Julien Margetts

IPC: G06F3/06 ,  G06F15/78

CPC classification number: G06F3/0656 ,  G06F3/0614 ,  G06F3/0659 ,  G06F3/0679 ,  G06F15/7807

Abstract: A solid-state drive having an integrated circuit comprising a controller that is configured to determine, for data transferred between a host interface of the integrated circuit and nonvolatile semiconductor storage device interface of the integrated circuit, the availability of an internal buffer of the integrated circuit to transparently accumulate the transferred data, and (i) if the internal buffer is available, accumulate the data from target nonvolatile semiconductor storage devices or the host in the internal buffer, or (ii) if the internal buffer is not available, accumulate the data unit from the target nonvolatile semiconductor storage devices or the host in an external buffer communicatively coupled to the controller, wherein the external buffer is external to the integrated circuit. The controller then provides the accumulated data to the respective interfaces to furnish a read or write request from the host.

公开(公告)号：US20250036311A1

公开(公告)日：2025-01-30

申请号：US18915048

申请日：2024-10-14

Applicant: Kioxia Corporation

Inventor： Paul Hanham ,  Julien Margetts ,  Matthew Stephens

IPC: G06F3/06

Abstract: Example implementations include a non-transitory processor-readable media comprising processor-readable instructions that when executed by at least one processor of a controller, causes the processor to generate at least one memory address corresponding respectively to at least one command block, the command block being associated with a command to a memory device, allocate the memory address to a buffer addressing unit associated with a host interface, the memory address including a buffer memory identifier associated with a buffer memory block and a buffer memory address associated with the buffer memory block, and update a request count associated with the buffer memory block by incrementing a reference counter associated with the buffer memory block.

公开(公告)号：US11847037B2

公开(公告)日：2023-12-19

申请号：US17022943

申请日：2020-09-16

Applicant: KIOXIA CORPORATION

Inventor： Paul Edward Hanham ,  Shigehiro Asano ,  Julien Margetts

IPC: G06F11/00 ,  G06F11/30 ,  G06F11/32 ,  G06F3/06 ,  G06F11/36

CPC classification number: G06F11/3075 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0683 ,  G06F11/3037 ,  G06F11/328 ,  G06F11/3656

Abstract: Example implementations include a method of receiving a host command identifier associated with a host command, determining a device command associated with the host command and a memory controller device, receiving a device command timestamp corresponding to a time of the determining the device command, and determining a debug record contemporaneously with the determining the device command, the debug record including the host command identifier, a device command identifier associated with the device command, and the device command timestamp. Example implementations also include a device operably coupled to a memory array, and with a memory controller device configured to receive a host command identifier associated with a host command, and configured to determine a device command associated with the host command and a memory controller device, and a debug record generator device operatively coupled to the memory controller device and configured to receive a device command timestamp corresponding to a time of the determined device command, and configured to determine a debug record contemporaneously with the determining the device command, the debug record including the host command identifier, a device command identifier associated with the device command, and the device command timestamp.

公开(公告)号：US11513683B2

公开(公告)日：2022-11-29

申请号：US17112094

申请日：2020-12-04

Applicant: Kioxia Corporation

Inventor： Shigehiro Asano ,  Julien Margetts ,  Philip David Rose

IPC: G06F3/06 ,  G06F12/02

Abstract: A data storage device capable of namespace re-sizing comprises a nonvolatile semiconductor storage device containing data accessed via a logical address that includes a namespace identifier and a logical block address, and a controller. The storage device can convert the namespace identifier to a base address using a first look up table. The storage device can further convert the logical block address to namespace allocation units of storage. The storage device can also determine a pointer using the base address, the namespace allocation units, and a second look up table. Further, the storage device can determine a full logical cluster address using the pointer.