公开(公告)号：US20230307415A1

公开(公告)日：2023-09-28

申请号：US17899260

申请日：2022-08-30

Applicant: KIOXIA CORPORATION

Inventor： Satoshi HONGO ,  Tatsuo MIGITA ,  Gen TOYOTA

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/29 ,  H01L23/48 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/291 ,  H01L23/481 ,  H01L23/3135 ,  H01L25/50 ,  H01L21/56

Abstract: According to one embodiment, a semiconductor device includes a base substrate with an interconnection layer and a plurality of chips stacked on the base substrate. A protective film is between each adjacent pair of chips in the plurality of chips stacked on the base substrate and on side surfaces of at least each chip in the plurality other than an uppermost chip in the stacked plurality of chips. A lowermost chip in the stacked plurality of chips has a metal pad electrically connected to the interconnection layer. Each chip in an adjacent pair of chips in the plurality of chips stacked on the base substrate has an electrode contacting an electrode of the other chip in the adjacent pair.

公开(公告)号：US20240321830A1

公开(公告)日：2024-09-26

申请号：US18596484

申请日：2024-03-05

Applicant: Kioxia Corporation

Inventor： Hayato FURUICHI ,  Yuusuke TAKANO ,  Tatsuo MIGITA

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/544

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/544 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2223/54426 ,  H01L2224/16145 ,  H01L2224/81 ,  H01L2224/94 ,  H01L2225/06541

Abstract: A manufacturing method of a semiconductor device, includes mounting on a first substrate a plurality of second substrates at a predetermined interval, the first substrate including a wiring layer, each of the second substrates including a plurality of semiconductor cells separated from each other by a boundary portion, forming a first recess on the first substrate between two of the second substrates that are adjacent to each other, cutting each of the second substrates along the boundary portion thereof to form a gap and a second recess on the first substrate through the gap, forming a sealing member on the first substrate, and cutting the first substrate together with the sealing member along lines extending along and inside the first and second recesses to individualize the semiconductor cells.

公开(公告)号：US20230101002A1

公开(公告)日：2023-03-30

申请号：US17694080

申请日：2022-03-14

Applicant: Kioxia Corporation

Inventor： Gen TOYOTA ,  Satoshi HONGO ,  Tatsuo MIGITA ,  Susumu YAMAMOTO ,  Tsutomu FUJITA ,  Eiichi SHIN ,  Yukio KATAMURA ,  Hideki MATSUSHIGE ,  Kazuki TAKAHASHI

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor device including a base substrate B, which includes wire layers, chips C1, C2, C3, C4, C5, and C6 provided on the base substrate B, and a protective film P provided on each of the side faces of the chips C1, C2, C3, C4, C5, and C6.

公开(公告)号：US20240284684A1

公开(公告)日：2024-08-22

申请号：US18426703

申请日：2024-01-30

Applicant: Kioxia Corporation

Inventor： Shinya WATANABE ,  Masahiro INOHARA ,  Tatsuo MIGITA ,  Masayuki MIURA

IPC: H10B80/00 ,  H01L21/78 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L21/78 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: A semiconductor device according to the present embodiment includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip has a first upper surface on which a first electrode pad is formed. The second semiconductor chip has a first lower surface on which a second electrode pad directly joined to the first electrode pad is formed and a second upper surface that is opposite the first lower surface and on which a third electrode pad is formed. The area of the first lower surface is smaller than the area of the first upper surface. The barycenter of the first lower surface and the barycenter of the first upper surface are located at different positions in the in-plane direction of the first upper surface.

公开(公告)号：US20230411330A1

公开(公告)日：2023-12-21

申请号：US17930688

申请日：2022-09-08

Applicant: Kioxia Corporation

Inventor： Masatoshi SHOMURA ,  Tatsuo MIGITA

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/11 ,  H01L25/0657 ,  H01L2924/1438 ,  H01L2224/11013 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2224/32145 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2224/10156 ,  H01L2224/13553 ,  H01L2224/13584 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2924/35121 ,  H01L2924/3511

Abstract: A semiconductor device according to the present embodiment includes an insulation member, a columnar electrode, a member, and an electrode pad. The insulation member has a first face. The columnar electrode penetrates the insulation member in a direction approximately perpendicular to the first face. The columnar electrode has a columnar electrode member and a first metal layer of at least one layer which covers an outer circumference of the columnar electrode member and which extends until becoming exposed from the first face. The member is provided on the first face and is arranged so as to overlap with at least a part of the first metal layer that is exposed from the first face as viewed from a direction approximately perpendicular to the first face. The electrode pad is provided on the first face so as to cover the member and is electrically connected to the columnar electrode member.

公开(公告)号：US20220013477A1

公开(公告)日：2022-01-13

申请号：US17189718

申请日：2021-03-02

Applicant: Kioxia Corporation

Inventor： Soichi HOMMA ,  Tatsuo MIGITA ,  Masayuki MIURA ,  Takeori MAEDA ,  Kazuhiro KATO ,  Susumu YAMAMOTO

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: A semiconductor device includes a semiconductor chip having a first face and a second face on an opposite side to the first face, and including semiconductor elements arranged on the first face. Columnar electrodes are arranged above the first face, and electrically connected to any of the semiconductor elements. A first member is located around the columnar electrodes above the first face. An insulant covers the columnar electrodes and the first member. The first member is harder than the columnar electrodes and the insulant. The first member and the columnar electrodes are exposed from a surface of the insulant.

公开(公告)号：US20210280416A1

公开(公告)日：2021-09-09

申请号：US17012337

申请日：2020-09-04

Applicant: Kioxia Corporation

Inventor： Tatsuo MIGITA

IPC: H01L21/02 ,  C23C14/06 ,  H01L23/13

Abstract: A manufacturing method of an embodiment of a semiconductor device, the manufacturing method includes: heating a second layer of a first member including a first layer, the second layer, and a third layer, in which the first layer includes a support layer, the second layer includes a compound containing carbon and at least one element selected from the group consisting of silicon and metals, the third layer includes a semiconductor layer and/or a wiring layer, and the second layer is located between the first layer and the third layer, and obtaining a second member in which a carbonaceous material layer is formed on a surface of the second layer and/or a carbonaceous material region is formed inside the second layer; and cleaving the second member from the carbonaceous material layer or the carbonaceous material region, and obtaining a third member including the third layer.