公开(公告)号：US20240304602A1

公开(公告)日：2024-09-12

申请号：US18669679

申请日：2024-05-21

Applicant: KIOXIA CORPORATION

Inventor： Tomoya SANUKI ,  Hiroshi MAEJIMA ,  Tetsuaki UTSUMI

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L24/08 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2225/06524 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a first voltage generator and a second voltage generator. The memory cell is provided above a substrate. The first voltage generator is provided between the substrate and the memory cell. The first voltage generator is configured to generate a first voltage to be supplied to the memory cell. The second voltage generator is provided between the substrate and the memory cell. The second voltage generator is configured to generate the first voltage and have a circuit configuration equivalent to the first voltage generator.

公开(公告)号：US20220399349A1

公开(公告)日：2022-12-15

申请号：US17548085

申请日：2021-12-10

Applicant: KIOXIA CORPORATION

Inventor： Nobuaki OKADA ,  Tetsuaki UTSUMI

IPC: H01L27/108 ,  H01L27/11 ,  H01L25/065

Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer, an element region provided on the semiconductor layer convexly, having a predetermined width in a first direction along a surface of the semiconductor layer, and extending in a second direction along the surface of the semiconductor layer and intersecting the first direction, a gate electrode arranged above the element region, a liner layer covering the gate electrode, and an element separation portion extends in the second direction on both sides of the element region in the first direction, and the liner layer continuously extends from the gate electrode to the element separation portion and the liner layer in the element separation portion lies below the element separation portion.

公开(公告)号：US20230074030A1

公开(公告)日：2023-03-09

申请号：US17984959

申请日：2022-11-10

Applicant: KIOXIA CORPORATION

Inventor： Hiroshi MAEJIMA ,  Toshifumi HASHIMOTO ,  Takashi MAEDA ,  Masumi SAITOH ,  Tetsuaki UTSUMI

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A semiconductor memory device includes a memory chip. The memory chip includes a first region including a plurality of first memory cells and second memory cells, a second region different from the first region, a plurality of first word lines stacked apart from each other in a first direction in the first and second regions, a first pillar including a first semiconductor layer extending through the first word lines, and a first insulator layer provided between the first semiconductor layer and the first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines, a first bonding pad in the second region, and a first transistor between the first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.

公开(公告)号：US20210091196A1

公开(公告)日：2021-03-25

申请号：US17013286

申请日：2020-09-04

Applicant: Kioxia Corporation

Inventor： Tetsuaki UTSUMI

IPC: H01L29/423

Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array disposed separately from the semiconductor substrate in a first direction; and first and second transistor arrays disposed on the semiconductor substrate. The semiconductor substrate includes a first region to a fourth region arranged in a second direction and a fifth region to an eighth region arranged in the second direction. These regions are each adjacent in a third direction. The memory cell array includes first conducting layers disposed in the first to fourth regions and second conducting layers disposed in the fifth to eighth regions. The first transistor array includes transistors connected to the plurality of first conducting layers via contacts disposed in the second region. The second transistor array includes transistors connected to the plurality of second conducting layers via contacts disposed in the seventh region.

公开(公告)号：US20250061953A1

公开(公告)日：2025-02-20

申请号：US18936629

申请日：2024-11-04

Applicant: Kioxia Corporation

Inventor： Tetsuaki UTSUMI

IPC: G11C16/30 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  H10B41/10 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor memory device includes word lines, first and second select gate lines, first and second semiconductor columns, first and second bit lines, and first and second transistors. The word lines are arranged in a first direction. The first and second select gate lines extend in a second direction and overlap with the word lines viewed from the first direction. The first and second select gate lines are arranged in the second direction. The first semiconductor column is opposed to the word lines and the first select gate line. The second semiconductor column is opposed to the word lines and the second select gate line. The first and second bit lines extend in a third direction and overlap with the first and second semiconductor columns viewed from the first direction. The first and second transistors are electrically connected to the first and second select gate lines.

公开(公告)号：US20230080259A1

公开(公告)日：2023-03-16

申请号：US18056508

申请日：2022-11-17

Applicant: Kioxia Corporation

Inventor： Tomoya SANUKI ,  Hiroshi MAEJIMA ,  Tetsuaki UTSUMI

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a first voltage generator and a second voltage generator. The memory cell is provided above a substrate. The first voltage generator is provided between the substrate and the memory cell. The first voltage generator is configured to generate a first voltage to be supplied to the memory cell. The second voltage generator is provided between the substrate and the memory cell. The second voltage generator is configured to generate the first voltage and have a circuit configuration equivalent to the first voltage generator.

公开(公告)号：US20230395671A1

公开(公告)日：2023-12-07

申请号：US18452965

申请日：2023-08-21

Applicant: KIOXIA CORPORATION

Inventor： Tetsuaki UTSUMI

IPC: H01L29/423

CPC classification number: H01L29/42324 ,  H01L29/4234

Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array disposed separately from the semiconductor substrate in a first direction; and first and second transistor arrays disposed on the semiconductor substrate. The semiconductor substrate includes a first region to a fourth region arranged in a second direction and a fifth region to an eighth region arranged in the second direction. These regions are each adjacent in a third direction. The memory cell array includes first conducting layers disposed in the first to fourth regions and second conducting layers disposed in the fifth to eighth regions. The first transistor array includes transistors connected to the plurality of first conducting layers via contacts disposed in the second region. The second transistor array includes transistors connected to the plurality of second conducting layers via contacts disposed in the seventh region.

公开(公告)号：US20230317709A1

公开(公告)日：2023-10-05

申请号：US18330258

申请日：2023-06-06

Applicant: Kioxia Corporation

Inventor： Nobuaki OKADA ,  Tetsuaki UTSUMI

IPC: H01L25/18 ,  H01L23/00 ,  G11C16/30

CPC classification number: H01L25/18 ,  H01L24/09 ,  H01L24/05 ,  H01L24/03 ,  G11C16/30 ,  H01L24/08 ,  G11C16/0483

Abstract: A semiconductor storage device includes first and second chips and first and second power supply electrodes. The first chip includes conductive layers arranged in a first direction, a semiconductor pillar extending in the first direction and facing the conductive layers, first contacts extending in the first direction and connected to the conductive layers, second contacts extending in the first direction and connected to a first power supply electrode, third contacts extending in the first direction, facing the second contacts in a direction crossing the first direction, and connected to the second power supply electrode, and first bonding electrodes connected to the first contacts. The second chip includes a semiconductor substrate, transistors provided on the semiconductor substrate, fourth contacts connected to the transistors, and second bonding electrodes connected to the fourth contacts. The first and second chips are bonded together so that respective first and second bonding electrodes are connected together.

公开(公告)号：US20220157389A1

公开(公告)日：2022-05-19

申请号：US17304789

申请日：2021-06-25

Applicant: Kioxia Corporation

Inventor： Tetsuaki UTSUMI

IPC: G11C16/30 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  G11C16/26 ,  G11C16/24 ,  G11C16/08

Abstract: A semiconductor memory device includes word lines, first and second select gate lines, first and second semiconductor columns, first and second bit lines, and first and second transistors. The word lines are arranged in a first direction. The first and second select gate lines extend in a second direction and overlap with the word lines viewed from the first direction. The first and second select gate lines are arranged in the second direction. The first semiconductor column is opposed to the word lines and the first select gate line. The second semiconductor column is opposed to the word lines and the second select gate line. The first and second bit lines extend in a third direction and overlap with the first and second semiconductor columns viewed from the first direction. The first and second transistors are electrically connected to the first and second select gate lines.

公开(公告)号：US20210383845A1

公开(公告)日：2021-12-09

申请号：US17410244

申请日：2021-08-24

Applicant: KIOXIA CORPORATION

Inventor： Tetsuaki UTSUMI

IPC: G11C7/10 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/408

Abstract: A semiconductor storage device includes a first input driver configured to receive a first signal from a memory controller, a second input driver configured to receive a chip enable signal from the memory controller, and a first control circuit. The first control circuit is configured to set the semiconductor storage device in an enabled state or a disabled state depending on whether or not the first signal which is received during a time period that starts with assertion of the chip enable signal and is prior to receipt of a command sequence, corresponds to a first chip address.