公开(公告)号：US11538791B2

公开(公告)日：2022-12-27

申请号：US16802462

申请日：2020-02-26

申请人： KIOXIA CORPORATION

发明人： Hiroshi Maejima ,  Toshifumi Hashimoto ,  Takashi Maeda ,  Masumi Saitoh ,  Tetsuaki Utsumi

IPC分类号： H01L25/065 ,  H01L25/18 ,  H01L23/00

摘要： A semiconductor memory device includes a memory chip. The memory chip includes a first region including a plurality of first memory cells and second memory cells, a second region different from the first region, a plurality of first word lines stacked apart from each other in a first direction in the first and second regions, a first pillar including a first semiconductor layer extending through the first word lines, and a first insulator layer provided between the first semiconductor layer and the first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines, a first bonding pad in the second region, and a first transistor between the first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.

公开(公告)号：US11728267B2

公开(公告)日：2023-08-15

申请号：US17159426

申请日：2021-01-27

申请人： Kioxia Corporation

发明人： Toshifumi Hashimoto ,  Jumpei Sato

IPC分类号： H01L23/528 ,  H01L23/522 ,  H10B43/35 ,  H10B43/40 ,  H10B41/35 ,  H10B41/40 ,  H01L23/532

CPC分类号： H01L23/5283 ,  H01L23/5226 ,  H01L23/53209 ,  H10B43/35 ,  H10B43/40 ,  H10B41/35 ,  H10B41/40

摘要： A semiconductor memory device is provided that includes a plurality of memory blocks, arranged in a second direction, that are spaced from a semiconductor substrate in a first direction intersecting with a surface of the semiconductor substrate; a first wiring that is farther from the semiconductor substrate than the plurality of memory blocks in the first direction; a second wiring that is closer to the semiconductor substrate than the plurality of memory blocks in the first direction; a first contact; a first transistor with a first active region disposed in the semiconductor substrate, the second wiring being electrically connected to a first memory block among the plurality of memory blocks via the first transistor; and a second transistor where the second wiring being electrically connected to a second memory block among the plurality of memory blocks via the second transistor.

公开(公告)号：US11017837B2

公开(公告)日：2021-05-25

申请号：US16812944

申请日：2020-03-09

申请人： KIOXIA CORPORATION

发明人： Toshifumi Hashimoto

IPC分类号： G11C16/26 ,  G11C11/4074 ,  G11C11/4076 ,  G11C16/34 ,  G11C11/409 ,  G11C11/408

摘要： According to one embodiment, a memory system includes: a semiconductor memory including a memory cell array, the memory cell array including a memory cell, and a controller configured to issue a first read command sequence after a lapse of a first time period from access to the semiconductor memory, and issue a second read command sequence after a lapse of a second time period from access to the semiconductor memory. When the controller issues the first read command sequence, the semiconductor memory applies a first voltage and a second voltage to the memory cell. When the controller issues the second read command sequence, the semiconductor memory applies a third voltage and a fourth voltage to the memory cell.

公开(公告)号：US11996143B2

公开(公告)日：2024-05-28

申请号：US17846889

申请日：2022-06-22

申请人： KIOXIA CORPORATION

发明人： Tomoki Nakagawa ,  Koji Kato ,  Toshifumi Hashimoto

IPC分类号： G11C16/30 ,  G11C5/14 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

CPC分类号： G11C11/5642 ,  G11C5/14 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/30

摘要： A semiconductor memory device includes a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, and a voltage generation circuit configured to independently control supply of voltages to the outer select gate lines and the inner select gate lines during an operation to read data stored in the memory cells.

公开(公告)号：US11929352B2

公开(公告)日：2024-03-12

申请号：US17984959

申请日：2022-11-10

申请人： KIOXIA CORPORATION

发明人： Hiroshi Maejima ,  Toshifumi Hashimoto ,  Takashi Maeda ,  Masumi Saitoh ,  Tetsuaki Utsumi

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L25/18

CPC分类号： H01L25/0657 ,  H01L24/08 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2225/06524 ,  H01L2924/1431 ,  H01L2924/14511

摘要： A semiconductor memory device includes a memory chip. The memory chip includes a first region including a plurality of first memory cells and second memory cells, a second region different from the first region, a plurality of first word lines stacked apart from each other in a first direction in the first and second regions, a first pillar including a first semiconductor layer extending through the first word lines, and a first insulator layer provided between the first semiconductor layer and the first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines, a first bonding pad in the second region, and a first transistor between the first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.

公开(公告)号：US11856774B2

公开(公告)日：2023-12-26

申请号：US17181027

申请日：2021-02-22

申请人： Kioxia Corporation

发明人： Toshifumi Hashimoto

IPC分类号： H10B43/27 ,  H01L29/792 ,  H10B43/10 ,  H01L23/00

CPC分类号： H10B43/27 ,  H01L24/46 ,  H01L29/792 ,  H10B43/10

摘要： A semiconductor memory device includes a substrate, a plurality of first conductive layers, a second conductive layer disposed at a position farther from or a position closer to the substrate than the plurality of first conductive layers, a first semiconductor column, a first electric charge accumulating film, a first wiring disposed at a position farther from or a position closer to the substrate than the plurality of first conductive layers and the second conductive layer, a first contact that is disposed between one end of the second conductive layer and the first semiconductor column and is electrically connected to the second conductive layer and the first wiring, and a second contact that is disposed between another end of the second conductive layer and the first semiconductor column and is electrically connected to the second conductive layer and the first wiring.

公开(公告)号：US20230307016A1

公开(公告)日：2023-09-28

申请号：US17807802

申请日：2022-06-20

申请人： Kioxia Corporation

发明人： Hiroshi Maejima ,  Toshifumi Hashimoto

IPC分类号： G11C7/10 ,  G11C7/08 ,  G11C16/16

CPC分类号： G11C7/1039 ,  G11C7/08 ,  G11C7/1063 ,  G11C7/109 ,  G11C16/16

摘要： A first conductor extends along first and second axes. A first memory pillar is provided in the first conductor and includes a first semiconductor and a charge accumulation layer. A second conductor extends along the second axis and is in contact with the first memory pillar. A third conductor extends along the first and second axes and is arranged with a distance from the first conductor along the second axis. A second memory pillar is provided in the third conductor and includes a second semiconductor and a charge accumulation layer. The fourth conductor extends along the second axis and is in contact with the second memory pillar. The fifth conductor extends along the second axis and is coupled to the first and second memory pillars.