公开(公告)号：US11903210B2

公开(公告)日：2024-02-13

申请号：US17376856

申请日：2021-07-15

Applicant: Kioxia Corporation

Inventor： Tetsuaki Utsumi

IPC: H10B43/30 ,  H01L25/065 ,  H10B43/20 ,  H10B43/27 ,  H10B43/50 ,  G11C5/04 ,  H01L23/00 ,  H01L29/792 ,  H01L21/822 ,  H01L21/28 ,  G11C29/02 ,  H10B43/40 ,  G11C29/04

CPC classification number: H10B43/30 ,  G11C5/04 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  H01L21/8221 ,  H01L24/16 ,  H01L25/0657 ,  H01L29/40117 ,  H01L29/792 ,  H10B43/20 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50 ,  G11C2029/0409 ,  H01L2224/16145 ,  H01L2225/06517

Abstract: A semiconductor memory device includes a semiconductor substrate, transistors formed in an upper surface of the semiconductor substrate, a stacked body provided on the semiconductor substrate, a first contact, and a second contact. The transistors are arranged along a first direction. A minimum period of an arrangement of the transistors is a first period. The stacked body includes electrode films. A configuration of a first portion of the stacked body is a staircase-like having terraces. A first region and a second region are set along the first direction in the first portion. A length in the first direction of the terrace disposed in the second region is longer than the first period. A length in the first direction of the terrace disposed in the first region is shorter than the first period.

公开(公告)号：US11929352B2

公开(公告)日：2024-03-12

申请号：US17984959

申请日：2022-11-10

Applicant: KIOXIA CORPORATION

Inventor： Hiroshi Maejima ,  Toshifumi Hashimoto ,  Takashi Maeda ,  Masumi Saitoh ,  Tetsuaki Utsumi

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L24/08 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2225/06524 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor memory device includes a memory chip. The memory chip includes a first region including a plurality of first memory cells and second memory cells, a second region different from the first region, a plurality of first word lines stacked apart from each other in a first direction in the first and second regions, a first pillar including a first semiconductor layer extending through the first word lines, and a first insulator layer provided between the first semiconductor layer and the first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines, a first bonding pad in the second region, and a first transistor between the first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.

公开(公告)号：US11862288B2

公开(公告)日：2024-01-02

申请号：US17410244

申请日：2021-08-24

Applicant: KIOXIA CORPORATION

Inventor： Tetsuaki Utsumi

IPC: G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C5/06

CPC classification number: G11C7/1063 ,  G11C5/06 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1087 ,  G11C11/408 ,  G11C11/4074

Abstract: A semiconductor storage device includes a first input driver configured to receive a first signal from a memory controller, a second input driver configured to receive a chip enable signal from the memory controller, and a first control circuit. The first control circuit is configured to set the semiconductor storage device in an enabled state or a disabled state depending on whether or not the first signal which is received during a time period that starts with assertion of the chip enable signal and is prior to receipt of a command sequence, corresponds to a first chip address.

公开(公告)号：US11508697B2

公开(公告)日：2022-11-22

申请号：US16806079

申请日：2020-03-02

Applicant: Kioxia Corporation

Inventor： Tomoya Sanuki ,  Hiroshi Maejima ,  Tetsuaki Utsumi

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a first voltage generator and a second voltage generator. The memory cell is provided above a substrate. The first voltage generator is provided between the substrate and the memory cell. The first voltage generator is configured to generate a first voltage to be supplied to the memory cell. The second voltage generator is provided between the substrate and the memory cell. The second voltage generator is configured to generate the first voltage and have a circuit configuration equivalent to the first voltage generator.

公开(公告)号：US20230395165A1

公开(公告)日：2023-12-07

申请号：US18363872

申请日：2023-08-02

Applicant: Kioxia Corporation

Inventor： Tetsuaki Utsumi

IPC: G11C16/30 ,  G11C16/08 ,  G11C16/26 ,  G11C16/24 ,  H10B41/10 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C16/30 ,  G11C16/08 ,  G11C16/26 ,  G11C16/24 ,  H10B43/40 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B41/10

Abstract: A semiconductor memory device includes word lines, first and second select gate lines, first and second semiconductor columns, first and second bit lines, and first and second transistors. The word lines are arranged in a first direction. The first and second select gate lines extend in a second direction and overlap with the word lines viewed from the first direction. The first and second select gate lines are arranged in the second direction. The first semiconductor column is opposed to the word lines and the first select gate line. The second semiconductor column is opposed to the word lines and the second select gate line. The first and second bit lines extend in a third direction and overlap with the first and second semiconductor columns viewed from the first direction. The first and second transistors are electrically connected to the first and second select gate lines.

公开(公告)号：US11488675B2

公开(公告)日：2022-11-01

申请号：US17304789

申请日：2021-06-25

Applicant: Kioxia Corporation

Inventor： Tetsuaki Utsumi

IPC: G11C16/30 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  G11C16/08 ,  H01L27/1157 ,  H01L27/11573 ,  G11C16/26 ,  G11C16/24 ,  H01L27/11565

Abstract: A semiconductor memory device includes word lines, first and second select gate lines, first and second semiconductor columns, first and second bit lines, and first and second transistors. The word lines are arranged in a first direction. The first and second select gate lines extend in a second direction and overlap with the word lines viewed from the first direction. The first and second select gate lines are arranged in the second direction. The first semiconductor column is opposed to the word lines and the first select gate line. The second semiconductor column is opposed to the word lines and the second select gate line. The first and second bit lines extend in a third direction and overlap with the first and second semiconductor columns viewed from the first direction. The first and second transistors are electrically connected to the first and second select gate lines.

公开(公告)号：US12232325B2

公开(公告)日：2025-02-18

申请号：US17462854

申请日：2021-08-31

Applicant: Kioxia Corporation

Inventor： Keisuke Nakatsuka ,  Yoshitaka Kubota ,  Tetsuaki Utsumi ,  Yoshiro Shimojo ,  Ryota Katsumata

IPC: H10B43/10 ,  H10B41/10 ,  H10B41/20 ,  H10B41/35 ,  H10B41/41 ,  H10B43/20 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.

公开(公告)号：US12159678B2

公开(公告)日：2024-12-03

申请号：US18363872

申请日：2023-08-02

Applicant: Kioxia Corporation

Inventor： Tetsuaki Utsumi

IPC: G11C16/30 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  H10B41/10 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor memory device includes word lines, first and second select gate lines, first and second semiconductor columns, first and second bit lines, and first and second transistors. The word lines are arranged in a first direction. The first and second select gate lines extend in a second direction and overlap with the word lines viewed from the first direction. The first and second select gate lines are arranged in the second direction. The first semiconductor column is opposed to the word lines and the first select gate line. The second semiconductor column is opposed to the word lines and the second select gate line. The first and second bit lines extend in a third direction and overlap with the first and second semiconductor columns viewed from the first direction. The first and second transistors are electrically connected to the first and second select gate lines.

公开(公告)号：US12132040B2

公开(公告)日：2024-10-29

申请号：US18330258

申请日：2023-06-06

Applicant: Kioxia Corporation

Inventor： Nobuaki Okada ,  Tetsuaki Utsumi

IPC: H01L25/18 ,  G11C16/04 ,  G11C16/30 ,  H01L23/00

CPC classification number: H01L25/18 ,  G11C16/30 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  G11C16/0483 ,  H01L2224/03452 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/08145 ,  H01L2224/09133 ,  H01L2224/09134 ,  H01L2224/09177 ,  H01L2224/09181 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor storage device includes first and second chips and first and second power supply electrodes. The first chip includes conductive layers arranged in a first direction, a semiconductor pillar extending in the first direction and facing the conductive layers, first contacts extending in the first direction and connected to the conductive layers, second contacts extending in the first direction and connected to a first power supply electrode, third contacts extending in the first direction, facing the second contacts in a direction crossing the first direction, and connected to the second power supply electrode, and first bonding electrodes connected to the first contacts. The second chip includes a semiconductor substrate, transistors provided on the semiconductor substrate, fourth contacts connected to the transistors, and second bonding electrodes connected to the fourth contacts. The first and second chips are bonded together so that respective first and second bonding electrodes are connected together.

公开(公告)号：US11769808B2

公开(公告)日：2023-09-26

申请号：US17374475

申请日：2021-07-13

Applicant: Kioxia Corporation

Inventor： Tetsuaki Utsumi

IPC: H01L29/423

CPC classification number: H01L29/42324 ,  H01L29/4234

Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array disposed separately from the semiconductor substrate in a first direction; and first and second transistor arrays disposed on the semiconductor substrate. The semiconductor substrate includes a first region to a fourth region arranged in a second direction and a fifth region to an eighth region arranged in the second direction. These regions are each adjacent in a third direction. The memory cell array includes first conducting layers disposed in the first to fourth regions and second conducting layers disposed in the fifth to eighth regions. The first transistor array includes transistors connected to the plurality of first conducting layers via contacts disposed in the second region. The second transistor array includes transistors connected to the plurality of second conducting layers via contacts disposed in the seventh region.