公开(公告)号：US20230154547A1

公开(公告)日：2023-05-18

申请号：US18156654

申请日：2023-01-19

Applicant: KIOXIA CORPORATION

Inventor： Takeshi HIOKA ,  Tsukasa KOBAYASHI ,  Koji KATO ,  Yuki SHIMIZU ,  Hiroshi MAEJIMA

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  H10B43/27 ,  H10B43/30

CPC classification number: G11C16/26 ,  G11C16/24 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  H10B43/27 ,  H10B43/30

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.

公开(公告)号：US20210383868A1

公开(公告)日：2021-12-09

申请号：US17409584

申请日：2021-08-23

Applicant: KIOXIA CORPORATION

Inventor： Yuki SHIMIZU ,  Yoshihiko KAMATA ,  Tsukasa KOBAYASHI ,  Hideyuki KATAOKA ,  Koji KATO ,  Takumi FUJIMOTO ,  Yoshinao SUZUKI ,  Yuui SHIMIZU

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C7/24 ,  G11C16/30 ,  G11C16/10 ,  G11C7/10 ,  G11C16/28

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.