公开(公告)号：US20230352099A1

公开(公告)日：2023-11-02

申请号：US18184893

申请日：2023-03-16

Applicant: KIOXIA CORPORATION

Inventor： Koji KATO ,  Yuki SHIMIZU ,  Shuhei OKETA

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  H01L23/528 ,  G11C16/10 ,  G11C16/32 ,  G11C16/30 ,  G11C5/06

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  H01L23/5283 ,  G11C16/10 ,  G11C16/32 ,  G11C16/30 ,  G11C5/06

Abstract: A semiconductor memory device includes: conductive layers including a first range and a second range; a first semiconductor layer opposed to the conductive layers in the first range; a second semiconductor layer opposed to the conductive layers in the second range; a first bit line electrically connected to one end of the first semiconductor layer; and a second bit line electrically connected to one end of the second semiconductor layer. When a sense time of the first bit line when a predetermined operation is performed on a first memory cell including a first electric charge accumulating portion is assumed to be a first operation parameter and a sense time of the second bit line when the predetermined operation is performed on a second memory cell including a second electric charge accumulating portion is assumed to be a second operation parameter, the second operation parameter differs from the first operation parameter.

公开(公告)号：US20230154547A1

公开(公告)日：2023-05-18

申请号：US18156654

申请日：2023-01-19

Applicant: KIOXIA CORPORATION

Inventor： Takeshi HIOKA ,  Tsukasa KOBAYASHI ,  Koji KATO ,  Yuki SHIMIZU ,  Hiroshi MAEJIMA

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  H10B43/27 ,  H10B43/30

CPC classification number: G11C16/26 ,  G11C16/24 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  H10B43/27 ,  H10B43/30

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.

公开(公告)号：US20220093174A1

公开(公告)日：2022-03-24

申请号：US17184246

申请日：2021-02-24

Applicant: KIOXIA CORPORATION

Inventor： Yuki SHIMIZU ,  Kosuke YANAGIDAIRA

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/26

Abstract: A semiconductor storage device includes a first plane storing user data and system information, a second plane storing the user data and the system information, a first latch circuit storing even-numbered bit data of the system information read from the first plane, a second latch circuit storing odd-numbered bit data of the system information read from the second plane, and a sequencer. The sequencer executes in parallel a first process of reading out the even-numbered bit data of the system information from the first plane and storing the read data in the first latch circuit and a second process of reading out the odd-numbered bit data of the system information from the second plane and storing the read data in the second latch circuit.

公开(公告)号：US20210383868A1

公开(公告)日：2021-12-09

申请号：US17409584

申请日：2021-08-23

Applicant: KIOXIA CORPORATION

Inventor： Yuki SHIMIZU ,  Yoshihiko KAMATA ,  Tsukasa KOBAYASHI ,  Hideyuki KATAOKA ,  Koji KATO ,  Takumi FUJIMOTO ,  Yoshinao SUZUKI ,  Yuui SHIMIZU

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C7/24 ,  G11C16/30 ,  G11C16/10 ,  G11C7/10 ,  G11C16/28

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.