公开(公告)号：US20150249159A1

公开(公告)日：2015-09-03

申请号：US14436241

申请日：2013-10-15

申请人： KABUSHIKI KAISHA KOBE SEIKO SHO (KOBE STEEL, LTD.) ,  Samsung Display Co., Ltd.

发明人： Hiroaki Tao ,  Takeaki Maeda ,  Aya Miki ,  Toshihiro Kugimiya ,  Byung Du Ahn ,  So Young Koo ,  Gun Hee Kim

IPC分类号： H01L29/786

CPC分类号： H01L29/78606 ,  H01L29/7869 ,  H01L29/78693

摘要： Provided is a thin film transistor wherein the shape of a protrusion formed on the interface between an oxide semiconductor layer and a protection film is suitably controlled, and stable characteristics are achieved. This thin film transistor is characterized in that: the thin film transistor has an oxide semiconductor layer formed of an oxide containing at least In, Zn and Sn as metal elements, and a protection film directly in contact with the oxide semiconductor layer; and the maximum height of a protrusion formed on the oxide semiconductor layer surface directly in contact with the protection film is less than 5 nm.

摘要翻译： 提供一种薄膜晶体管，其中形成在氧化物半导体层和保护膜之间的界面上的突起的形状被适当地控制，并且实现了稳定的特性。 该薄膜晶体管的特征在于：薄膜晶体管具有由至少含有In，Zn和Sn作为金属元素的氧化物和与氧化物半导体层直接接触的保护膜形成的氧化物半导体层; 在与保护膜直接接触的氧化物半导体层表面上形成的突起的最大高度小于5nm。

公开(公告)号：US09449990B2

公开(公告)日：2016-09-20

申请号：US14423838

申请日：2013-08-30

申请人： KOBE STEEL, LTD. ,  Samsung Display Co., Ltd.

发明人： Aya Miki ,  Shinya Morita ,  Hiroshi Goto ,  Hiroaki Tao ,  Toshihiro Kugimiya ,  Byung Du Ahn ,  Gun Hee Kim ,  Jin Hyun Park ,  Yeon Hong Kim

IPC分类号： H01L27/12 ,  H01L29/786 ,  H01L29/51 ,  H01L29/40 ,  H01L21/02

CPC分类号： H01L27/1225 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L29/408 ,  H01L29/4908 ,  H01L29/51 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

摘要： Provided is a thin film transistor which is provided with an oxide semiconductor thin film layer and has a threshold voltage that does not change much due to light, a bias stress or the like, thereby exhibiting excellent stress stability. A thin film transistor of the present invention is provided with a gate electrode, an oxide semiconductor layer composed of a single layer which is used as a channel layer, an etch stopper layer to protect a surface of the oxide semiconductor layer, a source-drain electrode, and a gate insulator layer arranged between the gate electrode and the channel layer. The metal elements constituting the oxide semiconductor layer comprise In, Zn and Sn. The hydrogen concentration in the gate insulator layer in direct contact with the oxide semiconductor layer is controlled to 4 atomic % or lower.

摘要翻译： 提供一种薄膜晶体管，其设置有氧化物半导体薄膜层，并且具有由于光，偏压应力等而不会变化太大的阈值电压，从而表现出优异的应力稳定性。 本发明的薄膜晶体管设置有栅电极，由用作沟道层的单层组成的氧化物半导体层，用于保护氧化物半导体层的表面的蚀刻停止层，源极 - 漏极 电极和布置在栅电极和沟道层之间的栅极绝缘体层。 构成氧化物半导体层的金属元素包括In，Zn和Sn。 与氧化物半导体层直接接触的栅极绝缘体层中的氢浓度被控制在4原子％以下。

公开(公告)号：US09324882B2

公开(公告)日：2016-04-26

申请号：US14721779

申请日：2015-05-26

申请人： Kobe Steel, Ltd. ,  Samsung Display Co., Ltd

发明人： Hiroshi Goto ,  Aya Miki ,  Tomoya Kishi ,  Kenta Hirose ,  Shinya Morita ,  Toshihiro Kugimiya ,  Byung Du Ahn ,  Gun Hee Kim ,  Yeon Hong Kim

IPC分类号： H01L29/786 ,  H01L27/12 ,  H01L21/02 ,  C23C14/08 ,  H01L29/24

CPC分类号： H01L29/78693 ,  C23C14/08 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/78606 ,  H01L29/78696

摘要： A thin film transistor containing at least, a gate electrode, a gate insulating film, an oxide semiconductor layer, source-drain electrode and a passivation film, in this order on a substrate. The oxide semiconductor layer is a laminate containing a first oxide semiconductor layer (IGZTO) and a second oxide semiconductor layer (IZTO). The second oxide semiconductor layer is formed on the gate insulating film, and the first oxide semiconductor layer is formed between the second oxide semiconductor layer and the passivation film. The contents of respective metal elements relative to the total amount of all the metal elements other than oxygen in the first oxide semiconductor layer are as follows; Ga: 8% or more and 30% or less; In: 25% or less, excluding 0%; Zn: 35% or more to 65% or less; and Sn: 5% or more to 30% or less.

摘要翻译： 至少在基板上至少含有栅极，栅极绝缘膜，氧化物半导体层，源极 - 漏极和钝化膜的薄膜晶体管。 氧化物半导体层是含有第一氧化物半导体层（IGZTO）和第二氧化物半导体层（IZTO）的层压体。 第二氧化物半导体层形成在栅极绝缘膜上，第一氧化物半导体层形成在第二氧化物半导体层和钝化膜之间。 各金属元素相对于第一氧化物半导体层中除氧以外的全部金属元素的总量的含量如下： Ga：8％以上且30％以下; 在：25％以下，不含0％; Zn：35％以上65％以下; 和Sn：5％以上至30％以下。

公开(公告)号：US20150228674A1

公开(公告)日：2015-08-13

申请号：US14423838

申请日：2013-08-30

申请人： KABUSHIKI KAISHA KOBE SEIKO SHO (KOBE STEEL, LTD.) ,  Samsung Display Co., Ltd.

发明人： Aya Miki ,  Shinya Morita ,  Hiroshi Goto ,  Hiroaki Tao ,  Toshihiro Kugimiya ,  Byung Du Ahn ,  Gun Hee Kim ,  Jin Hyun Park ,  Yeon Hong Kim

IPC分类号： H01L27/12 ,  H01L29/40 ,  H01L29/786

CPC分类号： H01L27/1225 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L29/408 ,  H01L29/4908 ,  H01L29/51 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

摘要： Provided is a thin film transistor which is provided with an oxide semiconductor thin film layer and has a threshold voltage that does not change much due to light, a bias stress or the like, thereby exhibiting excellent stress stability. A thin film transistor of the present invention is provided with a gate electrode, an oxide semiconductor layer composed of a single layer which is used as a channel layer, an etch stopper layer to protect a surface of the oxide semiconductor layer, a source-drain electrode, and a gate insulator layer arranged between the gate electrode and the channel layer. The metal elements constituting the oxide semiconductor layer comprise In, Zn and Sn. The hydrogen concentration in the gate insulator layer in direct contact with the oxide semiconductor layer is controlled to 4 atomic % or lower.

摘要翻译： 提供一种薄膜晶体管，其设置有氧化物半导体薄膜层，并且具有由于光，偏压应力等而不会变化太大的阈值电压，从而表现出优异的应力稳定性。 本发明的薄膜晶体管设置有栅电极，由用作沟道层的单层组成的氧化物半导体层，用于保护氧化物半导体层的表面的蚀刻停止层，源极 - 漏极 电极和布置在栅电极和沟道层之间的栅极绝缘体层。 构成氧化物半导体层的金属元素包括In，Zn和Sn。 与氧化物半导体层直接接触的栅极绝缘体层中的氢浓度被控制在4原子％以下。

公开(公告)号：US09070597B2

公开(公告)日：2015-06-30

申请号：US14262769

申请日：2014-04-27

申请人： Samsung Display Co., Ltd. ,  Kobe Steel, LTD.

发明人： Byung-Du Ahn ,  Gun-Hee Kim ,  Jun-Hyung Lim ,  Toshihiro Kugimiya ,  Hiroshi Goto ,  Aya Miki ,  Shinya Morita

IPC分类号： H01L29/00 ,  H01L27/12 ,  H01L29/786 ,  H01L29/66

CPC分类号： H01L27/1225 ,  H01L29/66969 ,  H01L29/78633 ,  H01L29/78693

摘要： A thin film transistor includes a gate electrode, a channel overlapped with the gate electrode, a source electrode contacting the channel, and a drain electrode spaced apart from the source electrode and contacting the channel. The channel includes indium-zinc-tin oxide sourced from a source including a single phase indium-zinc-tin oxide.

摘要翻译： 薄膜晶体管包括栅电极，与栅电极重叠的沟道，与沟道接触的源电极以及与源电极间隔开并与沟道接触的漏电极。 该通道包括源自包括单相铟 - 锌 - 锡氧化物的源的铟 - 锌 - 锡氧化物。

公开(公告)号：US10256091B2

公开(公告)日：2019-04-09

申请号：US15290715

申请日：2016-10-11

申请人： Kobe Steel, Ltd. ,  Samsung Display Co., Ltd.

发明人： Hiroaki Tao ,  Aya Miki ,  Shinya Morita ,  Satoshi Yasuno ,  Toshihiro Kugimiya ,  Jae Woo Park ,  Je Hun Lee ,  Byung Du Ahn ,  Gun Hee Kim

IPC分类号： H01L21/00 ,  H01L21/02 ,  H01L29/786 ,  H01L29/12 ,  H01L29/66 ,  H01L21/477 ,  G02F1/1368

摘要： The oxide of the present invention for thin-film transistors is an In—Zn—Sn-based oxide containing In, Zn, and Sn, wherein when the respective contents (atomic %) of metal elements contained in the In—Zn—Sn-based oxide are expressed by [Zn], [Sn], and [In], the In—Zn—Sn-based oxide fulfills the following expressions (2) and (4) when [In]/([In]+[Sn])≤0.5; or the following expressions (1), (3), and (4) when [In]/([In]+[Sn])>0.5. [In]/([In]+[Zn]+[Sn])≤0.3  (1), [In]/([In]+[Zn]+[Sn])≤1.4×{[Zn]/([Zn]+[Sn])}−0.5  (2), [Zn]/([In]+[Zn]+[Sn])≤0.83  (3), and 0.1≤[In]/([In]+[Zn]+[Sn])  (4). According to the present invention, oxide thin films for thin-film transistors can be obtained, which provide TFTs with excellent switching characteristics, and which have high sputtering rate in the sputtering and properly controlled etching rate in the wet etching.

公开(公告)号：US09553201B2

公开(公告)日：2017-01-24

申请号：US14179452

申请日：2014-02-12

申请人： Samsung Display Co., Ltd. ,  Kobe Steel, Ltd.

发明人： Byung Du Ahn ,  Ji Hun Lim ,  Gun Hee Kim ,  Kyoung Won Lee ,  Je Hun Lee ,  Hiroshi Goto ,  Aya Miki ,  Shinya Morita ,  Toshihiro Kugimiya ,  Yeon Hong Kim ,  Yeon Gon Mo ,  Kwang Suk Kim

IPC分类号： H01L27/14 ,  H01L29/786

CPC分类号： H01L29/7869 ,  H01L29/78696

摘要： The inventive concept relates to a thin film transistor and a thin film transistor array panel and, in detail, relates to a thin film transistor including an oxide semiconductor. A thin film transistor according to an exemplary embodiment of the inventive concept includes: a gate electrode; a gate insulating layer positioned on or under the gate electrode; a first semiconductor and a second semiconductor that overlap the gate electrode with the gate insulating layer interposed therebetween, the first semiconductor and the second semiconductor contacting each other; a source electrode connected to the second semiconductor; and a drain electrode connected to the second semiconductor and facing the source electrode, wherein the second semiconductor includes gallium (Ga) that is not included in the first semiconductor, and a content of gallium (Ga) in the second semiconductor is greater than 0 at. % and less than or equal to about 33 at. %.

摘要翻译： 本发明构思涉及薄膜晶体管和薄膜晶体管阵列面板，并且详细地涉及包括氧化物半导体的薄膜晶体管。 根据本发明构思的示例性实施例的薄膜晶体管包括：栅电极; 位于栅极电极上或下方的栅极绝缘层; 第一半导体和第二半导体，其与栅电极重叠，栅极绝缘层插入其间，第一半导体和第二半导体彼此接触; 连接到所述第二半导体的源电极; 和连接到第二半导体并面向源电极的漏电极，其中第二半导体包括不包括在第一半导体中的镓（Ga），并且第二半导体中的镓（Ga）的含量大于0 。 ％且小于或等于约33at。 ％。

公开(公告)号：US09508856B2

公开(公告)日：2016-11-29

申请号：US14436241

申请日：2013-10-15

申请人： KABUSHIKI KAISHA KOBE SEIKO SHO (KOBE STEEL, LTD.) ,  Samsung Display Co., Ltd.

发明人： Hiroaki Tao ,  Takeaki Maeda ,  Aya Miki ,  Toshihiro Kugimiya ,  Byung Du Ahn ,  So Young Koo ,  Gun Hee Kim

IPC分类号： H01L29/786

CPC分类号： H01L29/78606 ,  H01L29/7869 ,  H01L29/78693

摘要： Provided is a thin film transistor wherein the shape of a protrusion formed on the interface between an oxide semiconductor layer and a protection film is suitably controlled, and stable characteristics are achieved. This thin film transistor is characterized in that: the thin film transistor has an oxide semiconductor layer formed of an oxide containing at least In, Zn and Sn as metal elements, and a protection film directly in contact with the oxide semiconductor layer; and the maximum height of a protrusion formed on the oxide semiconductor layer surface directly in contact with the protection film is less than 5 nm.

摘要翻译： 提供一种薄膜晶体管，其中形成在氧化物半导体层和保护膜之间的界面上的突起的形状被适当地控制，并且实现了稳定的特性。 该薄膜晶体管的特征在于：薄膜晶体管具有由至少含有In，Zn和Sn作为金属元素的氧化物和与氧化物半导体层直接接触的保护膜形成的氧化物半导体层; 在与保护膜直接接触的氧化物半导体层表面上形成的突起的最大高度小于5nm。

公开(公告)号：US09343586B2

公开(公告)日：2016-05-17

申请号：US14399378

申请日：2013-06-06

申请人： Kobe Steel, Ltd.

发明人： Hiroshi Goto ,  Aya Miki ,  Tomoya Kishi ,  Kenta Hirose ,  Shinya Morita ,  Toshihiro Kugimiya

IPC分类号： H01L29/786 ,  H01L27/12 ,  H01L21/02 ,  C23C14/08 ,  H01L29/24

CPC分类号： H01L29/78693 ,  C23C14/08 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/78606 ,  H01L29/78696

摘要： Provided is a thin film transistor having an oxide semiconductor layer that has high mobility, excellent stress resistance, and good wet etching property. The thin film transistor comprises at least, a gate electrode, a gate insulating film, an oxide semiconductor layer, source-drain electrode and a passivation film, in this order on a substrate. The oxide semiconductor layer is a laminate comprising a first oxide semiconductor layer (IGZTO) and a second oxide semiconductor layer (IZTO). The second oxide semiconductor layer is formed on the gate insulating film, and the first oxide semiconductor layer is formed between the second oxide semiconductor layer and the passivation film. The contents of respective metal elements relative to the total amount of all the metal elements other than oxygen in the first oxide semiconductor layer are as follows; Ga: 5% or more; In: 25% or less (excluding 0%); Zn: 35 to 65%; and Sn: 8 to 30%.

摘要翻译： 提供了具有高迁移率，优异的耐应力和良好的湿蚀刻性能的氧化物半导体层的薄膜晶体管。 薄膜晶体管至少包括栅电极，栅极绝缘膜，氧化物半导体层，源 - 漏电极和钝化膜。 氧化物半导体层是包括第一氧化物半导体层（IGZTO）和第二氧化物半导体层（IZTO）的层压体。 第二氧化物半导体层形成在栅极绝缘膜上，第一氧化物半导体层形成在第二氧化物半导体层和钝化膜之间。 各金属元素相对于第一氧化物半导体层中除氧以外的全部金属元素的总量的含量如下： Ga：5％以上; 在：25％以下（不包括0％）; Zn：35〜65％ 和Sn：8〜30％。

公开(公告)号：US20150206978A1

公开(公告)日：2015-07-23

申请号：US14416213

申请日：2013-08-30

申请人： Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)

发明人： Aya Miki ,  Shinya Morita ,  Hiroshi Goto ,  Hiroaki Tao ,  Toshihiro Kugimiya

IPC分类号： H01L29/786 ,  H01L27/12 ,  H01L29/51

CPC分类号： H01L27/1225 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L29/408 ,  H01L29/4908 ,  H01L29/51 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

摘要： Provided is a thin film transistor comprising an oxide semiconductor thin film layer and has a threshold voltage that does not change much due to light, a bias stress or the like, thereby exhibiting excellent stress stability. A thin film transistor of the present invention is provided with: a gate electrode; two or more oxide semiconductor layers that are used as a channel layer; an etch stopper layer for protecting the surfaces of the oxide semiconductor layers; a source-drain electrode; and a gate insulator film interposed between the gate electrode and the channel layer. The metal elements constituting an oxide semiconductor layer that is in direct contact with the gate insulator film are In, Zn and Sn. The hydrogen concentration in the gate insulator film, which is in direct contact with the oxide semiconductor layer, is controlled to 4 atomic % or less.

摘要翻译： 提供了一种薄膜晶体管，其包括氧化物半导体薄膜层，并且具有由于光，偏压应力等而不会变化太大的阈值电压，从而表现出优异的应力稳定性。 本发明的薄膜晶体管设有：栅电极; 用作沟道层的两个或更多个氧化物半导体层; 用于保护氧化物半导体层的表面的蚀刻停止层; 源极 - 漏极电极; 以及插入在栅电极和沟道层之间的栅绝缘膜。 构成与栅极绝缘膜直接接触的氧化物半导体层的金属元素为In，Zn和Sn。 与氧化物半导体层直接接触的栅极绝缘膜的氢浓度被控制在4原子％以下。