公开(公告)号：US20140264514A1

公开(公告)日：2014-09-18

申请号：US14052129

申请日：2013-10-11

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Hyun Cheol KOO ,  Hyung-Jun KIM ,  Joon Yeon CHANG ,  Jun Woo CHOI ,  Suk Hee HAN

IPC: H01L27/092 ,  H01L27/22

CPC classification number: H01L29/0673 ,  H01L29/41725 ,  H01L29/4238 ,  H01L29/66984

Abstract: A complementary device including a gate electrode, a channel, a source electrode connected to the gate electrode and the channel, and a first drain electrode and a second drain electrode connected to the gate electrode and the channel is provided. The first/second drain electrode is formed so that, in accordance with a voltage applied to the gate electrode, electron spins injected into the source electrode are moved from the source electrode to the first/second drain electrode through the channel while rotating in a first/second direction. Directions of the electron spins that reach the first drain electrode and the second drain electrode are opposite to each other.

Abstract translation: 提供了包括栅电极，沟道，连接到栅电极和沟道的源电极以及连接到栅电极和沟道的第一漏电极和第二漏电极的互补器件。 第一/第二漏极形成为使得根据施加到栅电极的电压，注入到源电极的电子自旋通过沟道从源电极移动到第一/第二漏电极，同时在第一 /第二个方向。 到达第一漏电极和第二漏电极的电子自旋的方向彼此相反。

公开(公告)号：US20170301778A1

公开(公告)日：2017-10-19

申请号：US15487695

申请日：2017-04-14

Applicant: Korea Institute of Science and Technology

Inventor： Joon Yeon CHANG ,  Tae Eon PARK ,  Byoung Chul MIN ,  Hyun Cheol KOO ,  Suk Hee HAN

IPC: H01L29/66 ,  H01L29/47 ,  H01L29/06

CPC classification number: H01L29/66984 ,  B82Y10/00 ,  H01L27/222 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/417 ,  H01L29/41725 ,  H01L29/47 ,  H01L29/82 ,  H01L43/08

Abstract: A spin control electronic device operable at room temperature according to an embodiment of the present invention includes a transfer channel that includes a low-dimensional nanostructure, the nanostructure being located on a substrate, having an elongate shape in a first direction and having a cross section, cut along a second direction that is perpendicular to the first direction, in the shape of a triangle; a source electrode located on the substrate and intersecting the transfer channel, the source electrode covering part of the transfer channel; and a drain electrode spaced apart from the source electrode on the substrate, the drain electrode intersecting the transfer channel and covering part of the transfer channel.

公开(公告)号：US20140167814A1

公开(公告)日：2014-06-19

申请号：US14132492

申请日：2013-12-18

Applicant: Korea Institute Of Science And Technology

Inventor： Joon Yeon CHANG ,  Jin Ki HONG ,  Jin Dong SONG ,  Mark JOHNSON

IPC: H01L43/02 ,  H01L27/22 ,  H03K19/0175

CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1695 ,  H01L27/22 ,  H01L43/08 ,  H03K19/017581 ,  H03K19/16

Abstract: A non-volatile reconfigurable logic device executing logical operations and a memory function and controlled by a magnetic field is provided. The reconfigurable logic device includes i) at least one semiconductor device; and ii) a pair of magnetic field controlled devices respectively spaced apart from both sides of the semiconductor device and that are adapted to generate magnetic field leakage to control the semiconductor device. The semiconductor device includes i) a first semiconductor layer; and ii) a second semiconductor layer located on the first semiconductor layer. One of the first semiconductor layer and the second semiconductor layer is a p-type semiconductor layer and the other is an n-type semiconductor layer.

Abstract translation: 提供执行逻辑操作和存储功能并由磁场控制的非易失性可重构逻辑器件。 该可重构逻辑器件包括i）至少一个半导体器件; 以及ii）一对磁场控制装置，其分别与所述半导体器件的两侧间隔开并且适于产生磁场泄漏以控制所述半导体器件。 半导体器件包括i）第一半导体层; 以及ii）位于所述第一半导体层上的第二半导体层。 第一半导体层和第二半导体层之一是p型半导体层，另一个是n型半导体层。

公开(公告)号：US20220230060A1

公开(公告)日：2022-07-21

申请号：US17615394

申请日：2019-07-05

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Vladimir KORNIJCUK ,  Doo Seok JEONG ,  Joon Young KWAK ,  Jae Wook KIM ,  Jong Kil PARK ,  In Ho KIM ,  Jong Keuk PARK ,  Su Youn LEE ,  Yeon Joo JEONG ,  Joon Yeon CHANG

IPC: G06N3/063 ,  G06N3/04

Abstract: A neuromorphic device includes: a neuron block unit including a plurality of neurons; a synapse block unit including a plurality of synapses; and a topology block unit including a plurality of parallel Look-Up Table (LUT) modules including pre and post neuron elements configured with addresses of a presynaptic neuron and a postsynaptic neuron. Each of the plurality of neurons has an intrinsic address, each of the plurality of synapses has an intrinsic address. The parallel LUT module is partitioned based on a first synapse address among synapse addresses, and each of the partitions is indexed based on a second synapse address among the synapse addresses.

公开(公告)号：US20190035943A1

公开(公告)日：2019-01-31

申请号：US15920493

申请日：2018-03-14

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Hyun Cheol KOO ,  Hyung Jun KIM ,  Cha Un JANG ,  Joon Yeon CHANG ,  Suk Hee HAN ,  Joo Hyeon LEE

IPC: H01L29/82 ,  H01L29/66 ,  H01L29/43 ,  H01L29/205 ,  H01L27/08 ,  H03K19/08 ,  H03K19/20

Abstract: Provided is a reconfigurable logic device using an electrochemical potential. The device includes first and second semiconductor channels, where an effective magnetic field direction of a channel is controlled by a current direction and which are spaced apart from each other, a first ferromagnetic gate contacting the first semiconductor channel and a second ferromagnetic gate contacting the second semiconductor channel, where a magnetization direction is controlled by a gate voltage, and a control unit configured to calculate a difference value corresponding to a difference between a first determination value and a second determination value, and compare the difference value with a reference value to determine an output value.