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    SEMICONDUCTOR MEMORY DEVICE
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20160351628A1

    公开(公告)日：2016-12-01

    申请号：US14970082

    申请日：2015-12-15

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Mutsumi OKAJIMA ,  Atsushi OGA ,  Takeshi YAMAGUCHI ,  Hiroyuki ODE ,  Toshiharu TANAKA ,  Natsuki FUKUDA

    IPC分类号： H01L27/24 ,  H01L45/00

    CPC分类号： H01L27/11565 ,  H01L27/2427 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/06 ,  H01L45/1253 ,  H01L45/16

    摘要： In this semiconductor memory device, the first conducting layers are arrayed laminated in a first direction, and extend in a second direction intersecting with the first direction. The first conducting layers are arrayed in a third direction via interlayer insulating films. The third direction intersects with the first direction and the second direction. The interlayer insulating film is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer has an approximately circular cross-sectional shape intersecting with the first direction. The variable resistance layer surrounds a peripheral area of the second conducting layer, and is disposed at a position between the second conducting layer and the first conducting layer.

    摘要翻译： 在该半导体存储器件中，第一导电层沿第一方向排列并且沿与第一方向交叉的第二方向延伸。 第一导电层通过层间绝缘膜沿第三方向排列。 第三方向与第一方向和第二方向相交。 层间绝缘膜设置在沿第三方向排列的第一导电层之间，并沿第一方向延伸。 第二导电层设置在沿第三方向排列并沿第一方向延伸的第一导电层之间。 第二导电层具有与第一方向交叉的近似圆形的横截面形状。 可变电阻层围绕第二导电层的周边区域，并且设置在第二导电层和第一导电层之间的位置。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体存储器件及其制造方法

    公开(公告)号：US20160351624A1

    公开(公告)日：2016-12-01

    申请号：US14850527

    申请日：2015-09-10

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Atsushi OGA ,  Mutsumi OKAJIMA ,  Takeshi YAMAGUCHI ,  Hiroyuki ODE ,  Toshiharu TANAKA ,  Natsuki FUKUDA

    IPC分类号： H01L27/24 ,  H01L45/00

    CPC分类号： H01L27/2436 ,  H01L27/2454 ,  H01L27/2463 ,  H01L27/249 ,  H01L45/08 ,  H01L45/085 ,  H01L45/124 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1675 ,  H01L45/1683

    摘要： According to one embodiment, this semiconductor memory device includes first conducting layers, a memory layer, and second conducting layers. The first conducting layers are laminated at predetermined pitches in a first direction perpendicular to a substrate. The first conducting layers extend in a second direction parallel to the substrate. The second conducting layer extends in the first direction. A memory layer surrounds a circumference of the second conductive layer. The first conductive layers is in contact with a side surface of the second conductive layer via the memory layer. The memory cells are provided at intersections of the first conducting layers and the second conducting layer.

    摘要翻译： 根据一个实施例，该半导体存储器件包括第一导电层，存储层和第二导电层。 第一导电层以垂直于衬底的第一方向以预定间距层压。 第一导电层在与基板平行的第二方向上延伸。 第二导电层沿第一方向延伸。 存储层围绕第二导电层的圆周。 第一导电层经由存储层与第二导电层的侧表面接触。 存储单元设置在第一导电层和第二导电层的交点处。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME
    4.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 有权
    非易失性半导体存储器件及其控制方法

    公开(公告)号：US20160189776A1

    公开(公告)日：2016-06-30

    申请号：US14813523

    申请日：2015-07-30

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Takeshi TAKAGI ,  Masaki YAMATO ,  Hiroyuki ODE ,  Takeshi YAMAGUCHI ,  Toshiharu TANAKA

    IPC分类号： G11C13/00

    CPC分类号： G11C13/0064 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0052 ,  G11C2013/0083 ,  G11C2013/0092 ,  G11C2213/71

    摘要： A nonvolatile semiconductor memory device includes: a memory cell array; and a control circuit that controls a voltage applied to this memory cell array. The memory cell array includes: a first wiring line; a second wiring line intersecting the first wiring line; and a memory cell disposed at an intersection of these lines and including a variable resistance element. In a rewrite operation of the memory cell, the control circuit repeatedly perform a pulse application operation and a verify operation, the pulse application operation applying a pulse voltage to the memory cell, and the verify operation applying a first voltage to the memory cell to determine whether the rewrite operation has been completed or not. The control circuit is configured to, in a read operation from the memory cell, apply a second voltage to the memory cell. The second voltage has a voltage value larger than the first voltage.

    摘要翻译： 非易失性半导体存储器件包括：存储单元阵列; 以及控制电路，其控制施加到该存储单元阵列的电压。 存储单元阵列包括：第一布线; 与第一布线相交的第二布线; 以及设置在这些线的相交处并包括可变电阻元件的存储单元。 在存储单元的重写操作中，控制电路重复执行脉冲施加操作和验证操作，向存储单元施加脉冲电压的脉冲施加操作以及向存储器单元施加第一电压的校验操作以确定 重写操作是否已经完成。 控制电路被配置为在来自存储器单元的读取操作中向存储单元施加第二电压。 第二电压具有大于第一电压的电压值。

    NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME
    5.
    发明申请
    NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US20150155333A1

    公开(公告)日：2015-06-04

    申请号：US14208204

    申请日：2014-03-13

    申请人： Kabushiki Kaisha Toshiba

    发明人： Shigeki KOBAYASHI ,  Takeshi YAMAGUCHI ,  Masaki YAMATO ,  Yoshinori NAKAKUBO ,  Hiroyuki ODE

    IPC分类号： H01L27/24 ,  G11C13/00 ,  H01L45/00

    CPC分类号： H01L27/249 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0071 ,  H01L27/2454 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/148 ,  H01L45/149 ,  H01L45/16

    摘要： According to an embodiment, a nonvolatile memory device includes a first wiring extending to a first direction, a second wiring disposed on the first wiring in a second direction which is orthogonal to the first direction, a first insulating film provided between the first wiring and the second wiring, a bit line extending in the second direction, and a variable resistance film contacting an end portion of the first wiring, an end portion of the second wiring, and an end portion of the first insulating film. A dielectric constant of a center portion between the first and second wirings in the second direction is higher than at vicinities of the first and the second wirings. The variable resistance film is disposed between the bit line and the first wiring, between the bit line and the second wiring, and between the bit line and the first insulating film.

    摘要翻译： 根据实施例，非易失性存储器件包括延伸到第一方向的第一布线，在与第一方向正交的第二方向上布置在第一布线上的第二布线，设置在第一布线和第二布线之间的第一绝缘膜 第二布线，沿第二方向延伸的位线，以及与第一布线的端部，第二布线的端部和第一绝缘膜的端部接触的可变电阻膜。 第一和第二布线之间的第二方向上的中心部分的介电常数高于第一和第二布线附近的介电常数。 可变电阻膜设置在位线和第一布线之间，位线和第二布线之间以及位线和第一绝缘膜之间。

    MEMORY DEVICE
    8.
    发明申请
    MEMORY DEVICE 审中-公开
    内存设备

    公开(公告)号：US20150263278A1

    公开(公告)日：2015-09-17

    申请号：US14490938

    申请日：2014-09-19

    申请人： Kabushiki Kaisha Toshiba

    发明人： Hiroyuki ODE ,  Takeshi YAMAGUCHI ,  Shigeki KOBAYASHI ,  Masaki YAMATO ,  Yoshinori NAKAKUBO ,  Takeshi TAKAGI ,  Takayuki TSUKAMOTO

    IPC分类号： H01L45/00 ,  H01L27/24

    CPC分类号： H01L27/249 ,  H01L27/2454 ,  H01L45/04 ,  H01L45/1233

    摘要： A memory device according to an embodiment, includes a selection element, a first interconnection provided in a first direction when viewed from the selection element and extending in the first direction, a plurality of second interconnections provided in a second direction crossing the first direction when viewed from the first interconnection and arranged in the first direction, a memory element provided between the first interconnection and the second interconnection, and a high resistance component connected between the selection element and the first interconnection and having a resistivity higher than a resistivity of the first interconnection and a resistivity of the second interconnection.

    摘要翻译： 根据实施例的存储器件包括选择元件，当从选择元件观察并沿第一方向延伸时设置在第一方向上的第一互连件，当被观察时沿与第一方向交叉的第二方向设置的多个第二互连 设置在第一互连和第二互连之间的存储元件和连接在选择元件与第一互连之间并具有高于第一互连电阻率的电阻率的高电阻元件 和第二互连的电阻率。

    MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
    9.
    发明申请
    MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
    存储器件及其制造方法

    公开(公告)号：US20170062713A1

    公开(公告)日：2017-03-02

    申请号：US15013088

    申请日：2016-02-02

    申请人： Kabushiki Kaisha Toshiba

    发明人： Takeshi TAKAGI ,  Takeshi YAMAGUCHI ,  Masaki YAMATO ,  Hiroyuki ODE ,  Toshiharu TANAKA

    IPC分类号： H01L45/00 ,  H01L27/24

    CPC分类号： H01L45/1246 ,  H01L27/2427 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1641 ,  H01L45/1666

    摘要： According to one embodiment, A memory device includes a pillar, a first wiring, a second wiring, an insulating film provided between the first wiring and the second wiring, a first layer provided between the first wiring and the pillar in the second direction and including a first metal oxide containing a first metal and oxygen, a second layer provided between the second wiring and the pillar in the second direction and including the first metal oxide containing the first metal and oxygen, and an intermediate film provided between the pillar and the first layer and between the pillar and the second layer in the second direction and including a second metal oxide containing the first metal and oxygen. Concentration of oxygen contained in the first metal oxide is lower than concentration of oxygen contained in the second metal oxide.

    摘要翻译： 根据一个实施例，一种存储器件包括柱，第一布线，第二布线，设置在第一布线和第二布线之间的绝缘膜，第一层，沿第二方向设置在第一布线和柱之间，并且包括 含有第一金属和氧的第一金属氧化物，在第二方向上设置在第二布线和柱之间的第二层，并且包括含有第一金属和氧的第一金属氧化物，以及设置在柱与第一金属之间的中间膜 并且在第二方向上在柱和第二层之间并且包括含有第一金属和氧的第二金属氧化物。 第一金属氧化物中所含的氧的浓度低于第二金属氧化物中所含的氧浓度。