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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US09728585B1

    公开(公告)日：2017-08-08

    申请号：US15270682

    申请日：2016-09-20

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Masaki Yamato ,  Takeshi Yamaguchi ,  Takeshi Takagi ,  Natsuki Fukuda

    IPC分类号： H01L47/00 ,  H01L27/24 ,  H01L23/528 ,  H01L45/00

    CPC分类号： H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1683

    摘要： A semiconductor memory device according to an embodiment includes: a semiconductor substrate which extends in first and second directions that intersect each other; a plurality of first wiring lines which are arranged in a third direction that intersects the first direction and the second direction, and which extend in the first direction; a plurality of second wiring lines which are arranged in the first direction and extend in the third direction; and a plurality of memory cells disposed at intersections of the first wiring lines and the second wiring lines, one of the memory cells having a first film whose resistance changes electrically, a thickness in the second direction of the first film changing with respect to a change of position in the third direction, and the first films of two of the memory cells adjacent in the third direction being separated between the two memory cells.

    3D semiconductor memory device having variable resistance memory elements
    2.
    发明授权
    3D semiconductor memory device having variable resistance memory elements 有权
    具有可变电阻存储元件的3D半导体存储器件

    公开(公告)号：US09590016B2

    公开(公告)日：2017-03-07

    申请号：US14966184

    申请日：2015-12-11

    申请人： Kabushiki Kaisha Toshiba

    发明人： Masaki Yamato ,  Yasuhiro Nojiri ,  Shigeki Kobayashi ,  Hiroyuki Fukumizu ,  Takeshi Yamaguchi

    IPC分类号： H01L27/24 ,  H01L45/00

    CPC分类号： H01L27/249 ,  H01L27/2454 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

    摘要： A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position.

    摘要翻译： 多个第一导电层以垂直于基板的第一方向以预定间距堆叠。 在第一导电层的侧表面上共同提供存储层，并且用作存储单元。 第二导电层包括经由存储层与第一导电层的侧表面接触的第一侧表面，第二导电层沿第一方向延伸。 在第一位置处的第一侧表面的第二方向上的宽度小于在比第一位置低的第二位置处的第一侧表面的第二方向上的宽度。 第一导电层在第一位置的第一方向上的厚度大于第二导电层在第二位置的第一方向上的厚度。

    Multi-Level Memory Array Having Resistive Elements for Multi-Bit Data Storage
    4.
    发明申请
    Multi-Level Memory Array Having Resistive Elements for Multi-Bit Data Storage 有权
    具有用于多位数据存储的电阻元件的多级存储器阵列

    公开(公告)号：US20150310910A1

    公开(公告)日：2015-10-29

    申请号：US14627760

    申请日：2015-02-20

    申请人： Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

    发明人： Dipankar Pramanik ,  David E. Lazovsky ,  Tim Minvielle ,  Takeshi Yamaguchi

    IPC分类号： G11C11/56 ,  G11C13/00

    CPC分类号： G11C11/56 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/12 ,  G11C7/22 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/32 ,  G11C2213/33 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/145 ,  H01L45/1608

    摘要： A resistor array for multi-bit data storage without the need to increase the size of a memory chip or scale down the feature size of a memory cell contained within the memory chip is provided. The resistor array incorporates a number of discrete resistive elements to be selectively connected, in different series combinations, to at least one memory cell or memory device. In one configuration, by connecting each memory cell or device with at least one resistor array, a resistive switching layer found in the resistive switching memory element of the connected memory device is capable of being at multiple resistance states for storing multiple bits of digital information. During device programming operations, when a desired series combination of the resistive elements within the resistor array is selected, the resistive switching layer in the connected memory device can be in a desired resistance state.

    摘要翻译： 提供了用于多位数据存储的电阻器阵列，而不需要增加存储器芯片的尺寸或缩小存储器芯片中包含的存储器单元的特征尺寸。 电阻器阵列包括多个离散电阻元件，以便以不同的串联组合方式连接到至少一个存储器单元或存储器件。 在一种配置中，通过将每个存储器单元或设备连接至少一个电阻器阵列，在连接的存储器件的电阻式开关存储器元件中发现的电阻式开关层能够处于多个电阻状态，用于存储多位数字信息。 在器件编程操作期间，当选择电阻器阵列内的电阻元件的期望的串联组合时，连接的存储器件中的电阻式开关层可以处于期望的电阻状态。

    Atomic Layer Deposition of Metal Oxides for Memory Applications
    6.
    发明申请
    Atomic Layer Deposition of Metal Oxides for Memory Applications 有权
    用于存储器应用的金属氧化物的原子层沉积

    公开(公告)号：US20150179935A1

    公开(公告)日：2015-06-25

    申请号：US14624295

    申请日：2015-02-17

    申请人： Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

    发明人： Zhendong Hong ,  Vidyut Gopal ,  Imran Hashim ,  Randall J. Higuchi ,  Tim Minvielle ,  Hieu Pham ,  Takeshi Yamaguchi

    IPC分类号： H01L45/00

    CPC分类号： H01L45/146 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1616

    摘要： Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack which contains at least one hard metal oxide film (e.g., metal is completely oxidized or substantially oxidized) and at least one soft metal oxide film (e.g., metal is less oxidized than hard metal oxide). The soft metal oxide film is less electrically resistive than the hard metal oxide film since the soft metal oxide film is less oxidized or more metallic than the hard metal oxide film. In one example, the hard metal oxide film is formed by an ALD process utilizing ozone as the oxidizing agent while the soft metal oxide film is formed by another ALD process utilizing water vapor as the oxidizing agent.

    摘要翻译： 本发明的实施例一般涉及用于制造这种存储器件的非易失性存储器件和方法。 用于形成改进的存储器件（例如ReRAM单元）的方法提供优化的原子层沉积（ALD）工艺，用于形成金属氧化物膜堆叠，其包含至少一个硬金属氧化物膜（例如，金属被完全氧化或基本上被氧化 ）和至少一种软金属氧化物膜（例如，金属比硬金属氧化物氧化较少）。 由于软金属氧化物膜比硬金属氧化物膜氧化得更少或更金属，所以软金属氧化物膜的电阻小于硬金属氧化物膜。 在一个实例中，通过利用臭氧作为氧化剂的ALD工艺形成硬质金属氧化物膜，而通过利用水蒸汽作为氧化剂的另一ALD工艺形成软金属氧化物膜。

    Resistive random access memory cell having three or more resistive states
    8.
    发明授权
    Resistive random access memory cell having three or more resistive states 有权
    具有三个或更多个电阻状态的电阻随机存取存储单元

    公开(公告)号：US09001554B2

    公开(公告)日：2015-04-07

    申请号：US13738061

    申请日：2013-01-10

    申请人： Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

    发明人： Imran Hashim ,  Ryan C. Clarke ,  Nan Lu ,  Tim Minvielle ,  Takeshi Yamaguchi

    IPC分类号： H01L45/00 ,  G11C13/00

    CPC分类号： H01L45/146 ,  G11C11/56 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/77 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253

    摘要： Provided are resistive random access memory (ReRAM) cells, each having three or more resistive states and being capable of storing multiple bits of data, as well as methods of fabricating and operating such ReRAM cells. Such ReRAM cells or, more specifically, their resistive switching layer have wide range of resistive states and are capable of being very conductive (e.g., about 1 kOhm) in one state and very resistive (e.g., about 1 MOhm) in another state. In some embodiments, a resistance ratio between resistive states may be between 10 and 1,000 even up to 10,000. The resistive switching layers also allow establishing stable and distinct intermediate resistive states that may be assigned different data values. These layers may be configured to switching between their resistive states using fewer programming pulses than conventional systems by using specific materials, switching pluses, and resistive state threshold.

    摘要翻译： 提供了电阻随机存取存储器（ReRAM）单元，每个单元具有三个或更多个电阻状态，并且能够存储多个数据位，以及制造和操作这样的ReRAM单元的方法。 这样的ReRAM单元或更具体地，它们的电阻式开关层具有宽范围的电阻状态，并且在另一状态下能够在一种状态下非常导电（例如，约1kOhm），并且在另一状态下具有很强的电阻（例如约1MOhm）。 在一些实施例中，电阻状态之间的电阻比可以在10和1,000之间甚至高达10,000。 电阻式开关层还允许建立可分配不同数据值的稳定和不同的中间电阻状态。 这些层可以被配置为使用比常规系统更少的编程脉冲在其电阻状态之间切换，通过使用特定的材料，开关和电阻状态阈值。

    Transition metal oxide bilayers
    9.
    发明授权
    Transition metal oxide bilayers 有权
    过渡金属氧化物双层

    公开(公告)号：US08987697B2

    公开(公告)日：2015-03-24

    申请号：US14252285

    申请日：2014-04-14

    申请人： Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

    发明人： Hieu Pham ,  Vidyut Gopal ,  Imran Hashim ,  Tim Minvielle ,  Yun Wang ,  Takeshi Yamaguchi ,  Hong Sheng Yang

    IPC分类号： H01L29/02 ,  H01L45/00 ,  H01L27/24

    CPC分类号： H01L45/08 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641

    摘要： Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed. The nonvolatile memory element comprises a first electrode layer, a second electrode layer, and a plurality of layers of an oxide disposed between the first and second electrode layers. One of the oxide layers has linear resistance and substoichiometric composition, and the other oxide layer has bistable resistance and near-stoichiometric composition. Preferably, the sum of the two oxide layer thicknesses is between about 20 Å and about 100 Å, and the oxide layer with bistable resistance has a thickness between about 25% and about 75% of the total thickness. In one embodiment, the oxide layers are formed using reactive sputtering in an atmosphere with controlled flows of argon and oxygen.

    摘要翻译： 本发明的实施例包括非易失性存储器元件和包括非易失性存储元件的存储器件。 还公开了形成非易失性存储元件的方法。 非易失性存储元件包括第一电极层，第二电极层和设置在第一和第二电极层之间的多个氧化物层。 氧化物层中的一个具有线性电阻和亚化学计量组成，另一个氧化物层具有双稳态电阻和近化学计量组成。 优选地，两个氧化物层厚度的总和在约和之间，并且具有双稳态电阻的氧化物层具有在总厚度的约25％至约75％之间的厚度。 在一个实施例中，氧化物层在具有受控的氩气和氧气的气氛中使用反应溅射形成。