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    NONVOLATILE MEMORY DEVICE
    1.
    发明申请
    NONVOLATILE MEMORY DEVICE 审中-公开
    非易失性存储器件

    公开(公告)号：US20150249113A1

    公开(公告)日：2015-09-03

    申请号：US14293432

    申请日：2014-06-02

    申请人： Kabushiki Kaisha Toshiba

    发明人： Takeshi TAKAGI ,  Shigeki Kobayashi ,  Takeshi Yamaguchi

    IPC分类号： H01L27/24 ,  H01L45/00

    CPC分类号： H01L45/1233 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/15 ,  G11C2213/54 ,  G11C2213/55 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1246 ,  H01L45/146

    摘要： According to one embodiment, a nonvolatile memory device includes a first wiring, a second wiring, and a memory cell that is disposed at a position where the first and second wirings cross so as to be interposed between the first and second wirings. The memory cell includes a variable resistive layer and a tunnel barrier layer that is formed of an insulating film provided in contact with the variable resistive layer. The tunnel barrier layer is provided close to the first wiring to which a positive voltage with applied during set operation changing the variable resistive layer to a low-resistance state from a high-resistance state.

    摘要翻译： 根据一个实施例，非易失性存储器件包括第一布线，第二布线和存储单元，该第一布线，第二布线和存储单元布置在第一布线和第二布线交叉的位置处以插入在第一布线和第二布线之间。 存储单元包括由与可变电阻层接触的绝缘膜形成的可变电阻层和隧道势垒层。 隧道势垒层靠近第一布线设置，在设定操作期间施加的正电压将可变电阻层从高电阻状态改变为低电阻状态。

    MEMORY DEVICE
    3.
    发明申请
    MEMORY DEVICE 审中-公开
    内存设备

    公开(公告)号：US20150263278A1

    公开(公告)日：2015-09-17

    申请号：US14490938

    申请日：2014-09-19

    申请人： Kabushiki Kaisha Toshiba

    发明人： Hiroyuki ODE ,  Takeshi YAMAGUCHI ,  Shigeki KOBAYASHI ,  Masaki YAMATO ,  Yoshinori NAKAKUBO ,  Takeshi TAKAGI ,  Takayuki TSUKAMOTO

    IPC分类号： H01L45/00 ,  H01L27/24

    CPC分类号： H01L27/249 ,  H01L27/2454 ,  H01L45/04 ,  H01L45/1233

    摘要： A memory device according to an embodiment, includes a selection element, a first interconnection provided in a first direction when viewed from the selection element and extending in the first direction, a plurality of second interconnections provided in a second direction crossing the first direction when viewed from the first interconnection and arranged in the first direction, a memory element provided between the first interconnection and the second interconnection, and a high resistance component connected between the selection element and the first interconnection and having a resistivity higher than a resistivity of the first interconnection and a resistivity of the second interconnection.

    摘要翻译： 根据实施例的存储器件包括选择元件，当从选择元件观察并沿第一方向延伸时设置在第一方向上的第一互连件，当被观察时沿与第一方向交叉的第二方向设置的多个第二互连 设置在第一互连和第二互连之间的存储元件和连接在选择元件与第一互连之间并具有高于第一互连电阻率的电阻率的高电阻元件 和第二互连的电阻率。

    SEMICONDUCTOR MEMORY DEVICE
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20170263682A1

    公开(公告)日：2017-09-14

    申请号：US15227493

    申请日：2016-08-03

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Masanori KOMURA ,  Takeshi TAKAGI

    IPC分类号： H01L27/24 ,  H01L45/00 ,  H01L23/528

    CPC分类号： H01L27/249 ,  H01L23/528 ,  H01L27/2418 ,  H01L45/04 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146

    摘要： A semiconductor memory device according to an embodiment comprises: a semiconductor substrate which extends in first and second directions; first wiring lines which are arranged in a third direction, and which extend in the first direction; second wiring lines which are arranged in the first direction and extend in the third direction; and memory cells disposed at intersections of the first wiring lines and the second wiring lines, one of the memory cells including a first film and a second film whose permittivity is different from that of the first film which are stacked in the second direction between one of the first wiring lines and one of the second wiring lines, and the second films of two of the memory cells adjacent in the third direction being separated between the two memory cells.

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME
    7.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 有权
    非易失性半导体存储器件及其控制方法

    公开(公告)号：US20160189776A1

    公开(公告)日：2016-06-30

    申请号：US14813523

    申请日：2015-07-30

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Takeshi TAKAGI ,  Masaki YAMATO ,  Hiroyuki ODE ,  Takeshi YAMAGUCHI ,  Toshiharu TANAKA

    IPC分类号： G11C13/00

    CPC分类号： G11C13/0064 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0052 ,  G11C2013/0083 ,  G11C2013/0092 ,  G11C2213/71

    摘要： A nonvolatile semiconductor memory device includes: a memory cell array; and a control circuit that controls a voltage applied to this memory cell array. The memory cell array includes: a first wiring line; a second wiring line intersecting the first wiring line; and a memory cell disposed at an intersection of these lines and including a variable resistance element. In a rewrite operation of the memory cell, the control circuit repeatedly perform a pulse application operation and a verify operation, the pulse application operation applying a pulse voltage to the memory cell, and the verify operation applying a first voltage to the memory cell to determine whether the rewrite operation has been completed or not. The control circuit is configured to, in a read operation from the memory cell, apply a second voltage to the memory cell. The second voltage has a voltage value larger than the first voltage.

    摘要翻译： 非易失性半导体存储器件包括：存储单元阵列; 以及控制电路，其控制施加到该存储单元阵列的电压。 存储单元阵列包括：第一布线; 与第一布线相交的第二布线; 以及设置在这些线的相交处并包括可变电阻元件的存储单元。 在存储单元的重写操作中，控制电路重复执行脉冲施加操作和验证操作，向存储单元施加脉冲电压的脉冲施加操作以及向存储器单元施加第一电压的校验操作以确定 重写操作是否已经完成。 控制电路被配置为在来自存储器单元的读取操作中向存储单元施加第二电压。 第二电压具有大于第一电压的电压值。

    NONVOLATILE MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME
    8.
    发明申请
    NONVOLATILE MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 有权
    非易失性存储器件及其控制方法

    公开(公告)号：US20160019959A1

    公开(公告)日：2016-01-21

    申请号：US14635448

    申请日：2015-03-02

    申请人： Kabushiki Kaisha Toshiba

    发明人： Takeshi TAKAGI ,  Masaki Yamato ,  Hiroyuki Ode ,  Takeshi Yamaguchi ,  Toshiharu Tanaka

    IPC分类号： G11C13/00 ,  G06F11/07

    CPC分类号： G11C13/0069 ,  G06F11/073 ,  G06F11/076 ,  G06F11/0793 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2013/0092 ,  G11C2213/71

    摘要： A nonvolatile memory device comprises a memory cell comprising a variable resistance element connected between a couple of wirings and a control circuit applying a voltage between the couple of wirings connected to the memory cell. In data rewriting, the control circuit repeats a first voltage application step of applying a first write voltage between the couple of wirings and a first verify step of applying a first voltage lower than the first write voltage between the couple of wirings and comparing a cell current through the cell with a first threshold current, the steps repeated until a magnitude relation of the cell current and the first threshold current satisfies a first condition. If the first condition is satisfied, the circuit performs a second voltage application step of applying a second write voltage between the couple of wirings.

    摘要翻译： 非易失性存储器件包括存储单元，该存储单元包括连接在一对布线之间的可变电阻元件和在连接到存储单元的布线对之间施加电压的控制电路。 在数据重写中，控制电路重复第一电压施加步骤，在所述布线对之间施加第一写入电压，以及第一验证步骤，在所述布线对之间施加低于所述第一写入电压的第一电压，并且比较电池电流 通过具有第一阈值电流的单元，重复步骤，直到单元电流和第一阈值电流的大小关系满足第一条件。 如果满足第一条件，则电路执行施加第二写入电压在两对布线之间的第二电压施加步骤。

    MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
    9.
    发明申请
    MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
    存储器件及其制造方法

    公开(公告)号：US20170062713A1

    公开(公告)日：2017-03-02

    申请号：US15013088

    申请日：2016-02-02

    申请人： Kabushiki Kaisha Toshiba

    发明人： Takeshi TAKAGI ,  Takeshi YAMAGUCHI ,  Masaki YAMATO ,  Hiroyuki ODE ,  Toshiharu TANAKA

    IPC分类号： H01L45/00 ,  H01L27/24

    CPC分类号： H01L45/1246 ,  H01L27/2427 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1641 ,  H01L45/1666

    摘要： According to one embodiment, A memory device includes a pillar, a first wiring, a second wiring, an insulating film provided between the first wiring and the second wiring, a first layer provided between the first wiring and the pillar in the second direction and including a first metal oxide containing a first metal and oxygen, a second layer provided between the second wiring and the pillar in the second direction and including the first metal oxide containing the first metal and oxygen, and an intermediate film provided between the pillar and the first layer and between the pillar and the second layer in the second direction and including a second metal oxide containing the first metal and oxygen. Concentration of oxygen contained in the first metal oxide is lower than concentration of oxygen contained in the second metal oxide.

    摘要翻译： 根据一个实施例，一种存储器件包括柱，第一布线，第二布线，设置在第一布线和第二布线之间的绝缘膜，第一层，沿第二方向设置在第一布线和柱之间，并且包括 含有第一金属和氧的第一金属氧化物，在第二方向上设置在第二布线和柱之间的第二层，并且包括含有第一金属和氧的第一金属氧化物，以及设置在柱与第一金属之间的中间膜 并且在第二方向上在柱和第二层之间并且包括含有第一金属和氧的第二金属氧化物。 第一金属氧化物中所含的氧的浓度低于第二金属氧化物中所含的氧浓度。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    半导体存储器件及其制造方法

    公开(公告)号：US20160260479A1

    公开(公告)日：2016-09-08

    申请号：US14844424

    申请日：2015-09-03

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Hiroyuiki ODE ,  Takeshi YAMAGUCHI ,  Takeshi TAKAGI ,  Toshiharu TANAKA ,  Masaki YAMATO

    IPC分类号： G11C13/00 ,  H01L45/00

    CPC分类号： G11C13/0007 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/249 ,  H01L45/04 ,  H01L45/146 ,  H01L45/1616

    摘要： A semiconductor memory device comprises: a memory cell array 11; and a control circuit 16 that controls a voltage applied to the memory cell array 11. The memory cell array 11 includes: a plurality of word lines WL and bit lines BL that intersect each other; and a memory cell MC disposed at each of intersections of these word lines WL and bit lines BL. The memory cell MC includes a variable resistance element VR and a non-ohmic element NO. The variable resistance element VR is formed by a hafnium oxide crystalline film of monoclinic crystal in which a proportion of a component oriented in a (−1, 1, 1) plane and a (1, 1, 1) plane is 90% or more. This hafnium oxide crystalline film can be manufactured by a film-forming process by atomic layer deposition, employing an inorganic type hafnium precursor.

    摘要翻译： 半导体存储器件包括：存储单元阵列11; 以及控制施加到存储单元阵列11的电压的控制电路16.存储单元阵列11包括：相互相交的多个字线WL和位线BL; 以及设置在这些字线WL和位线BL的各交叉点处的存储单元MC。 存储单元MC包括可变电阻元件VR和非欧姆元件NO。 可变电阻元件VR由单斜晶体的氧化铪晶体膜形成，其中以（-1,1,1）面和（1,1,1）面取向的成分的比例为90％以上 。 该氧化铪结晶膜可以通过使用无机型铪前体的原子层沉积的成膜方法来制造。