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    Memory controller, storage device, and memory control method
    1.
    发明授权
    Memory controller, storage device, and memory control method 有权
    内存控制器，存储设备和内存控制方式

    公开(公告)号：US09043672B2

    公开(公告)日：2015-05-26

    申请号：US14017809

    申请日：2013-09-04

    申请人： Kabushiki Kaisha Toshiba

    发明人： Osamu Torii ,  Riki Suzuki ,  Ryo Yamaki ,  Naoaki Kokubun ,  Daisuke Miyashita ,  Kohei Oikawa

    IPC分类号： H03M13/00 ,  G06F11/10

    CPC分类号： G06F11/1068

    摘要： According to one embodiment, a memory controller includes: a first flash encoding unit that performs flash encoding on user data according to a first scheme to generate user data flash codes; an encoding unit that performs an error correction encoding process on the user data flash codes to generate parities; a second flash encoding unit that performs flash encoding on the parities according to a second scheme to generate parity flash codes; and a memory I/F that writes the user data flash codes and the parity flash codes to the nonvolatile memory.

    摘要翻译： 根据一个实施例，存储器控制器包括：第一闪存编码单元，其根据第一方案对用户数据执行闪存编码，以生成用户数据闪存代码; 对所述用户数据闪存代码执行纠错编码处理以生成奇偶校验的编码单元; 第二闪存编码单元，其根据第二方案对奇偶校验执行闪存编码以产生奇偶校验闪存代码; 以及将用户数据闪存代码和奇偶校验闪存代码写入非易失性存储器的存储器I / F。

    STORAGE DEVICE, MEMORY CONTROLLER AND MEMORY CONTROL METHOD
    2.
    发明申请
    STORAGE DEVICE, MEMORY CONTROLLER AND MEMORY CONTROL METHOD 审中-公开
    存储设备，存储器控制器和存储器控制方法

    公开(公告)号：US20160071597A1

    公开(公告)日：2016-03-10

    申请号：US14624938

    申请日：2015-02-18

    申请人： Kabushiki Kaisha Toshiba

    发明人： Naoaki KOKUBUN ,  Osamu Torii ,  Riki Suzuki

    IPC分类号： G11C16/10 ,  G06F11/10 ,  G11C16/26

    CPC分类号： G06F11/1072 ,  G06F11/1048 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/28 ,  G11C16/3495 ,  G11C2211/5641

    摘要： According to an embodiment, a storage device includes a nonvolatile memory which includes a plurality of memory cells and a memory controller which controls writing on the nonvolatile memory. In a case where an exhaustion degree of the memory cell of the nonvolatile memory is less than a threshold, the memory controller performs a fractional-bit writing in which the number of threshold regions of the memory cell is set to Z (where, Z is a positive value not a power of two). In a case where the exhaustion degree of the memory cell is equal to or higher than the threshold, the memory controller performs an integer-bit writing in which the number of threshold regions of the memory cell is set to 2m (where, 2m is smaller than Z).

    摘要翻译： 根据实施例，存储装置包括包括多个存储单元的非易失性存储器和控制对非易失性存储器的写入的存储器控​​制器。 在非易失性存储器的存储单元的耗尽度小于阈值的情况下，存储器控制器执行将存储单元的阈值区域的数量设定为Z（其中，Z为 一个正值不是二的幂）。 在存储单元的耗尽程度等于或高于阈值的情况下，存储器控制器执行将存储单元的阈值区域的数量设置为2m（其中，2m更小）的整数位写入 比Z）。

    Memory system and method of controlling nonvolatile memory
    3.
    发明授权
    Memory system and method of controlling nonvolatile memory 有权
    内存系统和非易失性存储器的控制方法

    公开(公告)号：US09251892B1

    公开(公告)日：2016-02-02

    申请号：US14636685

    申请日：2015-03-03

    申请人： Kabushiki Kaisha Toshiba

    发明人： Shohei Asami ,  Toshikatsu Hida ,  Tokumasa Hara ,  Riki Suzuki

    IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C11/56

    CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C2211/5634

    摘要： According to an embodiment, a controller specifies a first voltage range that has a first distribution quantity, a second voltage range that is adjacent to a lower voltage side of the first voltage range, and a third voltage range that is adjacent to a higher voltage side of the first voltage range. The first distribution quantity is a minimum value of the memory cells. The controller determines a read voltage by using the first voltage range, a first representative voltage value in the first voltage range, the first distribution quantity, a second distribution quantity corresponding to the second voltage range, and a third distribution quantity corresponding to the third voltage range.

    摘要翻译： 根据实施例，控制器指定具有第一分配量的第一电压范围，与第一电压范围的较低电压侧相邻的第二电压范围和与较高电压侧相邻的第三电压范围 的第一电压范围。 第一分配量是存储单元的最小值。 控制器通过使用第一电压范围，第一电压范围中的第一代表性电压值，第一分配量，对应于第二电压范围的第二分配量和对应于第三电压的第三分配量来确定读取电压 范围。

    Storage device, memory controller and memory control method
    4.
    发明授权
    Storage device, memory controller and memory control method 有权
    存储设备，内存控制器和内存控制方式

    公开(公告)号：US09171629B1

    公开(公告)日：2015-10-27

    申请号：US14478292

    申请日：2014-09-05

    申请人： Kabushiki Kaisha Toshiba

    发明人： Naoaki Kokubun ,  Osamu Torii ,  Kohsuke Harada ,  Riki Suzuki

    IPC分类号： G11C11/34 ,  G11C16/10

    CPC分类号： G11C16/10 ,  G06F11/1072 ,  G11C11/5628 ,  G11C2211/5641

    摘要： According to one embodiment, a storage device comprises a nonvolatile memory and a memory controller that performs reading and writing data from and into the nonvolatile memory. A number, not being 2n, of threshold areas can be set in the memory cells of the nonvolatile memory. The memory controller performs first writing based on first data value assignment, which sets 2n data values to correspond to 2n threshold areas, in first-time writing into a first memory cell of the nonvolatile memory and performs second writing on the first memory cell after the first writing without erasing data based on second data value assignment, which sets 2n data values to correspond to 2n threshold areas including threshold areas not used in the first data value assignment.

    摘要翻译： 根据一个实施例，存储设备包括非易失性存储器和执行从非易失性存储器读取数据和向非易失性存储器写入数据的存储器控​​制器。 可以在非易失性存储器的存储单元中设置不是2n的阈值区域的数目。 存储器控制器基于第一数据值分配执行首次写入，其首先将2n个数据值设置为对应于2n个阈值区域，首次写入到非易失性存储器的第一存储单元中，并且在第一存储器单元之后执行第二写入 首先写入而不擦除基于第二数据值分配的数据，其将2n个数据值设置为对应于包括在第一数据值分配中未使用的阈值区域的2n个阈值区域。

    Memory address management system and method
    5.
    发明授权
    Memory address management system and method 有权
    内存地址管理系统和方法

    公开(公告)号：US09158678B2

    公开(公告)日：2015-10-13

    申请号：US13893615

    申请日：2013-05-14

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Riki Suzuki ,  Shohei Asami ,  Toshikatsu Hida ,  Hiroshi Yao ,  Kazuhiro Fukutomi

    IPC分类号： G06F12/02 ,  G06F12/10

    CPC分类号： G06F12/0246 ,  G06F12/1027 ,  G06F2212/7201

    摘要： According to one embodiment, a memory system includes a nonvolatile memory including first blocks configured to store an address indicating a data storage position, and second blocks configured to store the data, a first table configured to store a first address including first information and second information, the second information indicating a data storage position in the first block, and a second table configured to convert the first information into third information, the first information having a first data size by which one entry of the second table can be identified, the third information having a second data size which is larger than the first data size and by which one of the first blocks and the second blocks can be identified.

    摘要翻译： 根据一个实施例，存储器系统包括：非易失性存储器，包括被配置为存储指示数据存储位置的地址的第一块和被配置为存储数据的第二块的第一块;被配置为存储包括第一信息和第二信息的第一地址的第一表 所述第二信息指示所述第一块中的数据存储位置;以及第二表，被配置为将所述第一信息转换为第三信息，所述第一信息具有可识别所述第二表的一个条目的第一数据大小，所述第三信息 具有大于第一数据大小的第二数据大小的信息以及可以识别第一块和第二块中的哪一个。

    MEMORY SYSTEM
    6.
    发明申请
    MEMORY SYSTEM 审中-公开

    公开(公告)号：US20170262192A1

    公开(公告)日：2017-09-14

    申请号：US15264119

    申请日：2016-09-13

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Sayano AGA ,  Toshikatsu Hida ,  Riki Suzuki

    IPC分类号： G06F3/06 ,  G06F12/10 ,  G06F12/02

    CPC分类号： G06F3/0611 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/10 ,  G06F2212/1024 ,  G06F2212/2022

    摘要： According to one embodiment, a memory system includes a first memory as a nonvolatile memory storing first data, second data as a translation table for accessing the first data, third data, fourth data as a translation table for accessing the third data, and including two memory cell arrays which are accessible in parallel, a second memory in which the second and fourth data is storable, and which stores a management table for managing information about whether the second and fourth data is stored in the second memory, a controller checking whether the second and fourth data is stored in the second memory based on the management table, a third memory storing an order of executing commands to be issued to the first memory, and a scheduler scheduling the order based on a result of the checking, two of a first command for reading the first data, a second command for reading the second data, a third command for reading the third data and a fourth command for reading the fourth data being executed in parallel in the order.

    Storage device
    10.
    发明授权
    Storage device 有权
    储存设备

    公开(公告)号：US08976589B2

    公开(公告)日：2015-03-10

    申请号：US13925017

    申请日：2013-06-24

    申请人： Kabushiki Kaisha Toshiba

    发明人： Riki Suzuki ,  Shohei Asami ,  Toshikatsu Hida

    IPC分类号： G11C11/34 ,  G11C29/04

    CPC分类号： G11C29/04 ,  G06F12/0246 ,  G06F2212/7211

    摘要： According to one embodiment, a storage device includes a nonvolatile memory and a controller. The nonvolatile memory includes blocks which store data. Each of the blocks is an erase unit. The controller controls an operation of the nonvolatile memory. The controller executes writes and erases with respect to a first block of the blocks in the nonvolatile memory for the first number of times during a first period. The controller executes writes and erases with respect to other blocks for the second number of times smaller than the first number of times during the first period.

    摘要翻译： 根据一个实施例，存储设备包括非易失性存储器和控制器。 非易失性存储器包括存储数据的块。 每个块是擦除单元。 控制器控制非易失性存储器的操作。 在第一时段期间，控制器相对于非易失性存储器中的第一块的第一块执行写入和擦除。 控制器执行相对于其他块的写入和擦除次数小于第一个周期中的第一次次数。