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公开(公告)号：US09275727B2
公开(公告)日：2016-03-01
申请号：US14627760
申请日：2015-02-20
CPC分类号： G11C11/56 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/12 , G11C7/22 , G11C11/5685 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2213/32 , G11C2213/33 , G11C2213/34 , G11C2213/72 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L45/145 , H01L45/1608
摘要： A resistor array for multi-bit data storage without the need to increase the size of a memory chip or scale down the feature size of a memory cell contained within the memory chip is provided. The resistor array incorporates a number of discrete resistive elements to be selectively connected, in different series combinations, to at least one memory cell or memory device. In one configuration, by connecting each memory cell or device with at least one resistor array, a resistive switching layer found in the resistive switching memory element of the connected memory device is capable of being at multiple resistance states for storing multiple bits of digital information. During device programming operations, when a desired series combination of the resistive elements within the resistor array is selected, the resistive switching layer in the connected memory device can be in a desired resistance state.
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2.发明授权公开(公告)号：US08748237B2
公开(公告)日：2014-06-10
申请号：US14064787
申请日：2013-10-28
发明人： Dipankar Pramanik , Tony P. Chiang , Mankoo Lee
IPC分类号： H01L29/8605
CPC分类号： H01L45/14 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2013/0073 , G11C2013/0078 , G11C2013/0092 , G11C2213/76 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/10 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/16
摘要： A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.
摘要翻译： 提供了并入电阻式开关存储单元或装置中以形成具有改进的器件性能和寿命的存储器件的电阻器结构。 电阻器结构可以是设计成减小流过存储器件的最大电流的两端结构。 还提供了一种用于制造这种存储器件的方法。 该方法包括沉积电阻器结构并沉积存储器件的电阻式开关存储单元的可变电阻层，其中电阻器结构与可变电阻层串联设置以限制存储器件的开关电流。 电阻器结构的结合对于获得满足各种类型的存储器件的开关规范的期望的器件开关电流水平是非常有用的。 存储器件可以形成为可用于各种电子器件的大容量非易失性存储器集成电路的一部分。
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公开(公告)号：US08735217B2
公开(公告)日：2014-05-27
申请号：US14017942
申请日：2013-09-04
发明人： Hieu Pham , Vidyut Gopal , Imran Hashim , Tim Minvielle , Dipankar Pramanik , Yun Wang , Takeshi Yamaguchi , Hong Sheng Yang
IPC分类号： H01L29/02
CPC分类号： C23C14/345 , C23C14/0042 , C23C14/0641 , C23C14/083 , C23C14/225 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1608 , H01L45/1616 , H01L45/1625
摘要： A nonvolatile memory element is disclosed comprising a first electrode, a near-stoichiometric metal oxide memory layer having bistable resistance, and a second electrode in contact with the near-stoichiometric metal oxide memory layer. At least one electrode is a resistive electrode comprising a sub-stoichiometric transition metal nitride or oxynitride, and has a resistivity between 0.1 and 10 Ωcm. The resistive electrode provides the functionality of an embedded current-limiting resistor and also serves as a source and sink of oxygen vacancies for setting and resetting the resistance state of the metal oxide layer. Novel fabrication methods for the second electrode are also disclosed.
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4.发明申请Atomic Layer Deposition of Hafnium and Zirconium Oxides for Memory Applications 审中-公开用于记忆应用的铪和氧化锆的原子层沉积公开(公告)号：US20130334484A1
公开(公告)日：2013-12-19
申请号：US13972587
申请日：2013-08-21
发明人： Yun Wang , Tony P. Chiang , Vidyut Gopal , Imran Hashim , Dipankar Pramanik
IPC分类号： H01L45/00
CPC分类号： H01L45/146 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/1616
摘要： Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack having a metal oxide buffer layer disposed on or over a metal oxide bulk layer. The metal oxide bulk layer contains a metal-rich oxide material and the metal oxide buffer layer contains a metal-poor oxide material. The metal oxide bulk layer is less electrically resistive than the metal oxide buffer layer since the metal oxide bulk layer is less oxidized or more metallic than the metal oxide buffer layer. In one example, the metal oxide bulk layer contains a metal-rich hafnium oxide material and the metal oxide buffer layer contains a metal-poor zirconium oxide material.
摘要翻译： 本发明的实施例一般涉及用于制造这种存储器件的非易失性存储器件和方法。 用于形成改进的存储器件（例如ReRAM单元）的方法提供优化的原子层沉积（ALD）工艺，用于形成金属氧化物膜堆叠，其具有设置在金属氧化物本体层上或其上的金属氧化物缓冲层。 金属氧化物本体层含有富金属氧化物材料，金属氧化物缓冲层含有贫金属氧化物。 由于金属氧化物本体层比金属氧化物缓冲层氧化较少或更金属，所以金属氧化物本体层的电阻小于金属氧化物缓冲层的电阻。 在一个实例中，金属氧化物本体层含有富金属氧化铪材料，金属氧化物缓冲层含有贫金属氧化锆材料。
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公开(公告)号：US20130221315A1
公开(公告)日：2013-08-29
申请号：US13721310
申请日：2012-12-20
发明人： Yun Wang , Tony P. Chiang , Imran Hashim , Tim Minvielle , Dipankar Pramanik , Takeshi Yamaguchi
IPC分类号： H01L45/00
CPC分类号： H01L45/12 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/10 , H01L45/1233 , H01L45/1253 , H01L45/146
摘要： A resistor structure incorporated into a resistive switching memory cell with improved performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory cell. A method is also provided for making such a memory cell. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory cell, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory cell. The incorporation of the resistor structure is very useful in obtaining desirable levels of switching currents that meet the switching specification of various types of memory cells. The memory cells may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.
摘要翻译： 提供了一种结合到具有改进的性能和寿命的电阻式开关存储单元中的电阻器结构。 电阻器结构可以是设计成减小流过存储器单元的最大电流的两端结构。 还提供了一种用于制造这种存储单元的方法。 该方法包括沉积电阻器结构并沉积存储单元的电阻式开关存储单元的可变电阻层，其中电阻器结构与可变电阻层串联布置以限制存储单元的开关电流。 电阻器结构的结合对于获得满足各种类型的存储器单元的开关规范的期望的开关电流水平是非常有用的。 存储单元可以形成为可用于各种电子设备的大容量非易失性存储器集成电路的一部分。
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6.发明授权Multi-level memory array having resistive elements for multi-bit data storage 有权具有用于多位数据存储的电阻元件的多级存储器阵列公开(公告)号：US08995166B2
公开(公告)日：2015-03-31
申请号：US13721279
申请日：2012-12-20
CPC分类号： G11C11/56 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/12 , G11C7/22 , G11C11/5685 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2213/32 , G11C2213/33 , G11C2213/34 , G11C2213/72 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L45/145 , H01L45/1608
摘要： A resistor array for multi-bit data storage without the need to increase the size of a memory chip or scale down the feature size of a memory cell contained within the memory chip is provided. The resistor array incorporates a number of discrete resistive elements to be selectively connected, in different series combinations, to at least one memory cell or memory device. In one configuration, by connecting each memory cell or device with at least one resistor array, a resistive switching layer found in the resistive switching memory element of the connected memory device is capable of being at multiple resistance states for storing multiple bits of digital information. During device programming operations, when a desired series combination of the resistive elements within the resistor array is selected, the resistive switching layer in the connected memory device can be in a desired resistance state.
摘要翻译： 提供了用于多位数据存储的电阻器阵列，而不需要增加存储器芯片的尺寸或缩小存储器芯片中包含的存储器单元的特征尺寸。 电阻器阵列包括多个离散电阻元件，以便以不同的串联组合方式连接到至少一个存储器单元或存储器件。 在一种配置中，通过将每个存储器单元或设备连接至少一个电阻器阵列，在连接的存储器件的电阻式开关存储器元件中发现的电阻式开关层能够处于多个电阻状态，用于存储多位数字信息。 在器件编程操作期间，当选择电阻器阵列内的电阻元件的期望的串联组合时，连接的存储器件中的电阻式开关层可以处于期望的电阻状态。
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公开(公告)号：US08975114B2
公开(公告)日：2015-03-10
申请号：US13804318
申请日：2013-03-14
CPC分类号： H01L45/1253 , H01L27/101 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process.
摘要翻译： 本发明的实施例一般涉及用于制造这种存储器件的存储器件和方法。 在一个实施例中，一种用于制造电阻式开关存储器件的方法包括在设置在衬底上的下电极上沉积金属层，并将该金属层暴露于活性氧源，同时将衬底加热到约300的范围内的氧化温度 约600℃，并且在氧化过程中从金属层的上部形成金属氧化物层。 下部电极含有硅材料，金属层含有铪或锆。 在氧化处理之后，该方法还包括将衬底加热至大于600℃至约850℃的范围内的退火温度，同时在硅化期间从金属层的下部形成金属硅化物层 处理。
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8.发明申请公开(公告)号：US20150056749A1
公开(公告)日：2015-02-26
申请号：US14506298
申请日：2014-10-03
发明人： Yun Wang , Tony P. Chiang , Vidyut Gopal , Imran Hashim , Dipankar Pramanik
CPC分类号： H01L45/145 , C23C16/40 , C23C16/45525 , H01L21/02175 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/02192 , H01L21/02194 , H01L21/022 , H01L21/0228 , H01L27/2463 , H01L45/08 , H01L45/1266 , H01L45/146 , H01L45/1608 , H01L45/1616
摘要： Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies. Therefore, the metal oxide film stacks have improved switching performance and reliability during memory cell applications compared to traditional hafnium oxide based stacks of previous memory cells.
摘要翻译： 本发明的实施例一般涉及非易失性存储器件，例如ReRAM单元，以及用于制造这种存储器件的方法，其包括用于形成金属氧化物膜堆叠的优化的原子层沉积（ALD）工艺。 金属氧化物膜堆叠包含设置在金属氧化物主体层上的金属氧化物耦合层，每个层具有不同的晶粒结构/尺寸。 设置在金属氧化物层之间的界面有助于氧空位移动。 在许多示例中，与垂直于电极界面延伸的体膜中的晶粒相反，界面是不对齐的晶粒界面，其包含平行于电极界面延伸的许多晶界。 因此，氧空缺在切换期间被捕获和释放，而空位明显损失。 因此，与以前的存储单元的传统的基于氧化铪的堆叠相比，金属氧化物膜堆叠在存储单元应用中具有改进的开关性能和可靠性。
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公开(公告)号：US20140117303A1
公开(公告)日：2014-05-01
申请号：US13722314
申请日：2012-12-20
发明人： Yun Wang , Tony P. Chiang , Imran Hashim , Tim Minvielle , Dipankar Pramanik , Takeshi Yamaguchi
IPC分类号： H01L45/00
CPC分类号： H01L45/1608 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C2213/56 , G11C2213/76 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/16
摘要： Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from alloys of transition metals. Some examples of such alloys include chromium containing alloys that may also include nickel, aluminum, and/or silicon. Other examples include tantalum and/or titanium containing alloys that may also include a combination of silicon and carbon or a combination of aluminum and nitrogen. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature processing. In some embodiments, the breakdown voltage of a current limiting layer is at least about 8V. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layers while maintaining their performance.
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10.发明授权公开(公告)号：US08975727B2
公开(公告)日：2015-03-10
申请号：US13721310
申请日：2012-12-20
发明人： Yun Wang , Tony P. Chiang , Imran Hashim , Tim Minvielle , Dipankar Pramanik , Takeshi Yamaguchi
IPC分类号： H01L29/8605 , H01L45/00 , H01L27/24
CPC分类号： H01L45/12 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/10 , H01L45/1233 , H01L45/1253 , H01L45/146
摘要： A resistor structure incorporated into a resistive switching memory cell with improved performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory cell. A method is also provided for making such a memory cell. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory cell, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory cell. The incorporation of the resistor structure is very useful in obtaining desirable levels of switching currents that meet the switching specification of various types of memory cells. The memory cells may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.
摘要翻译： 提供了一种结合到具有改进的性能和寿命的电阻式开关存储单元中的电阻器结构。 电阻器结构可以是设计成减小流过存储器单元的最大电流的两端结构。 还提供了一种用于制造这种存储单元的方法。 该方法包括沉积电阻器结构并沉积存储单元的电阻式开关存储单元的可变电阻层，其中电阻器结构与可变电阻层串联布置以限制存储单元的开关电流。 电阻器结构的结合对于获得满足各种类型的存储器单元的开关规范的期望的开关电流水平是非常有用的。 存储单元可以形成为可用于各种电子设备的大容量非易失性存储器集成电路的一部分。
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