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1.发明申请Technique for creating different mechanical strain in different channel regions by forming an etch stop layer stack having differently modified intrinsic stress 有权通过形成具有不同修正的固有应力的蚀刻停止层堆叠在不同沟道区域中产生不同的机械应变的技术公开(公告)号：US20060091471A1
公开(公告)日：2006-05-04
申请号：US11150635
申请日：2005-06-10
IPC分类号： H01L29/78 , H01L21/8238 , H01L21/469
CPC分类号： H01L29/4933 , H01L21/31116 , H01L21/7624 , H01L21/823807 , H01L21/823835 , H01L29/665 , H01L29/7843
摘要： A technique is provided that allows the formation of contact etch stop layers having different intrinsic stress for different transistors, while substantially avoiding any device degradation owing to the partial removal of the contact etch stop layer. Hereby, an additional thin etch stop layer is provided prior to the formation of the contact etch stop layers, thereby substantially maintaining the integrity of metal silicide regions, when a portion of an initially deposited contact etch stop layer is removed.
摘要翻译： 提供了允许形成对于不同晶体管具有不同固有应力的接触蚀刻停止层的技术，同时基本上避免了由于部分去除接触蚀刻停止层而导致的任何器件劣化。 因此，在形成接触蚀刻停止层之前，提供另外的薄蚀刻停止层，从而当初始沉积的接触蚀刻停止层的一部分被去除时，基本上保持金属硅化物区域的完整性。
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2.发明授权Technique for creating different mechanical strain in different channel regions by forming an etch stop layer stack having differently modified intrinsic stress 有权通过形成具有不同修正的固有应力的蚀刻停止层堆叠在不同沟道区域中产生不同的机械应变的技术公开(公告)号：US07396718B2
公开(公告)日：2008-07-08
申请号：US11150635
申请日：2005-06-10
IPC分类号： H01L21/8238
CPC分类号： H01L29/4933 , H01L21/31116 , H01L21/7624 , H01L21/823807 , H01L21/823835 , H01L29/665 , H01L29/7843
摘要： A technique is provided that allows the formation of contact etch stop layers having different intrinsic stress for different transistors, while substantially avoiding any device degradation owing to the partial removal of the contact etch stop layer. Hereby, an additional thin etch stop layer is provided prior to the formation of the contact etch stop layers, thereby substantially maintaining the integrity of metal silicide regions, when a portion of an initially deposited contact etch stop layer is removed.
摘要翻译： 提供了允许形成对于不同晶体管具有不同固有应力的接触蚀刻停止层的技术，同时基本上避免了由于部分去除接触蚀刻停止层而导致的任何器件劣化。 因此，在形成接触蚀刻停止层之前，提供另外的薄蚀刻停止层，从而当初始沉积的接触蚀刻停止层的一部分被去除时，基本上保持金属硅化物区域的完整性。
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3.发明申请METHOD FOR REDUCING RESIST POISONING DURING PATTERNING OF SILICON NITRIDE LAYERS IN A SEMICONDUCTOR DEVICE 有权在半导体器件中用于降低硅氮化物层的方式减少耐药性的方法公开(公告)号：US20080081480A1
公开(公告)日：2008-04-03
申请号：US11742878
申请日：2007-05-01
申请人： Kai Frohberg , Volker Grimm , Sven Mueller , Matthias Lehr , Ralf Richter , Jochen Klais , Martin Mazur , Heike Salz , Joerg Hohage , Matthias Schaller
发明人： Kai Frohberg , Volker Grimm , Sven Mueller , Matthias Lehr , Ralf Richter , Jochen Klais , Martin Mazur , Heike Salz , Joerg Hohage , Matthias Schaller
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/76802 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/823807 , H01L29/665 , H01L29/7833 , H01L29/7843
摘要： By performing a plasma treatment for efficiently sealing the surface of a stressed dielectric layer containing silicon nitride, an enhanced performance during the patterning of contact openings may be achieved, since nitrogen-induced resist poisoning may be significantly reduced during the selective patterning of stressed layers of different types of intrinsic stress.
摘要翻译： 通过进行等离子体处理以有效地密封包含氮化硅的应力介电层的表面，可以实现在接触开口的图案化期间提高的性能，因为在所选择的图形化应力层的选择性图案化期间可以显着降低氮诱导的抗蚀剂中毒 不同类型的内在应力。
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4.发明授权Method for reducing resist poisoning during patterning of silicon nitride layers in a semiconductor device 有权用于在半导体器件中的氮化硅层的图案化期间减少抗蚀剂中毒的方法公开(公告)号：US07550396B2
公开(公告)日：2009-06-23
申请号：US11742878
申请日：2007-05-01
申请人： Kai Frohberg , Volker Grimm , Sven Mueller , Matthias Lehr , Ralf Richter , Jochen Klais , Martin Mazur , Heike Salz , Joerg Hohage , Matthias Schaller
发明人： Kai Frohberg , Volker Grimm , Sven Mueller , Matthias Lehr , Ralf Richter , Jochen Klais , Martin Mazur , Heike Salz , Joerg Hohage , Matthias Schaller
IPC分类号： H01L21/461
CPC分类号： H01L21/31144 , H01L21/76802 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/823807 , H01L29/665 , H01L29/7833 , H01L29/7843
摘要： By performing a plasma treatment for efficiently sealing the surface of a stressed dielectric layer containing silicon nitride, an enhanced performance during the patterning of contact openings may be achieved, since nitrogen-induced resist poisoning may be significantly reduced during the selective patterning of stressed layers of different types of intrinsic stress.
摘要翻译： 通过进行等离子体处理以有效地密封包含氮化硅的应力介电层的表面，可以实现在接触开口的图案化期间提高的性能，因为在所选择的图形化应力层的选择性图案化期间可以显着降低氮诱导的抗蚀剂中毒 不同类型的内在应力。
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5.发明授权Void sealing in a dielectric material of a contact level of a semiconductor device comprising closely spaced transistors 有权在包括紧密间隔的晶体管的半导体器件的接触电平的电介质材料中的空隙密封公开(公告)号：US08129276B2
公开(公告)日：2012-03-06
申请号：US12693545
申请日：2010-01-26
申请人： Ralf Richter , Kai Frohberg , Holger Schuehrer
发明人： Ralf Richter , Kai Frohberg , Holger Schuehrer
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/823475 , H01L21/7682 , H01L21/76829 , H01L21/76831 , H01L21/76897 , H01L21/823425
摘要： In sophisticated semiconductor devices, a contact structure may be formed on the basis of a void positioned between closely spaced transistor elements wherein disadvantageous metal migration along the void may be suppressed by sealing the voids after etching a contact opening and prior to filling in the contact metal. Consequently, significant yield losses may be avoided in well-established dual stress liner approaches while, at the same time, superior device performance may be achieved.
摘要翻译： 在复杂的半导体器件中，可以基于位于紧密间隔的晶体管元件之间的空隙形成接触结构，其中沿着空隙的不利的金属迁移可以通过在蚀刻接触开口之后并且在填充接触金属之前密封空隙来抑制 。 因此，在已建立的双重应力衬垫方法中可以避免显着的屈服损失，同时可以实现优异的装置性能。
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6.发明授权Method and semiconductor structure for monitoring the fabrication of interconnect structures and contacts in a semiconductor device 有权用于监测半导体器件中互连结构和触点的制造的方法和半导体结构公开(公告)号：US07491555B2
公开(公告)日：2009-02-17
申请号：US11419782
申请日：2006-05-23
申请人： Matthias Lehr , Kai Frohberg , Holger Schuehrer
发明人： Matthias Lehr , Kai Frohberg , Holger Schuehrer
IPC分类号： H01L21/66
CPC分类号： H01L22/32 , H01L21/76816 , H01L21/76843
摘要： By measuring an electric characteristic of a test pad that is connected to a plurality of test vias formed in accordance with a specified process flow for forming contacts and vias of a semiconductor device, one or more process specific parameters may quantitatively be estimated. Thus, a fast and precise measurement method for contacts and vias is provided in a non-destructive manner.
摘要翻译： 通过测量连接到根据用于形成半导体器件的触点和通孔的指定工艺流程形成的多个测试通孔的测试焊盘的电特性，可以定量地估计一个或多个工艺特定参数。 因此，以非破坏性的方式提供用于触点和通孔的快速且精确的测量方法。
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7.发明授权公开(公告)号：US07259091B2
公开(公告)日：2007-08-21
申请号：US11112509
申请日：2005-04-22
IPC分类号： H01L21/4763
CPC分类号： H01L21/02063 , H01L21/76802 , H01L21/76814
摘要： By performing a wet chemical process after etching a via, contaminations may be removed and a thin passivation layer may be formed that may then be readily removed in a subsequent sputter etch process for forming a barrier/adhesion layer. In a particular embodiment, the wet chemical process may be performed on the basis of fluoric acid and triazole or a compound thereof.
摘要翻译： 通过在蚀刻通孔之后进行湿化学处理，可以去除污染物，并且可以形成薄的钝化层，然后可以在随后的溅射蚀刻工艺中容易地去除以形成阻挡层/粘附层。 在一个具体实施方案中，湿化学方法可以基于氟酸和三唑或其化合物进行。
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8.发明申请公开(公告)号：US20060024951A1
公开(公告)日：2006-02-02
申请号：US11112509
申请日：2005-04-22
IPC分类号： H01L21/4763
CPC分类号： H01L21/02063 , H01L21/76802 , H01L21/76814
摘要： By performing a wet chemical process after etching a via, contaminations may be removed and a thin passivation layer may be formed that may then be readily removed in a subsequent sputter etch process for forming a barrier/adhesion layer. In a particular embodiment, the wet chemical process may be performed on the basis of fluoric acid and triazole or a compound thereof.
摘要翻译： 通过在蚀刻通孔之后进行湿化学处理，可以去除污染物，并且可以形成薄的钝化层，然后可以在随后的溅射蚀刻工艺中容易地去除以形成阻挡层/粘附层。 在一个具体实施方案中，湿化学方法可以基于氟酸和三唑或其化合物进行。
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9.发明申请Method of forming a field effect transistor comprising a stressed channel region 失效形成包括应力沟道区域的场效应晶体管的方法公开(公告)号：US20060076652A1
公开(公告)日：2006-04-13
申请号：US11125046
申请日：2005-05-09
申请人： Joerg Hohage , Hartmut Ruelke , Kai Frohberg
发明人： Joerg Hohage , Hartmut Ruelke , Kai Frohberg
IPC分类号： H01L23/58 , H01L21/469
CPC分类号： H01L29/7843 , H01L21/823412 , H01L21/823437 , H01L29/665
摘要： A semiconductor structure comprises a transistor element formed in a substrate. A stressed layer is formed over the transistor element. The stressed layer has a predetermined tensile intrinsic stress of about 900 MPa or more. Due to this high intrinsic stress, the stressed layer exerts considerable elastic forces to the channel region of the transistor element. Thus, tensile stress is created in the channel region. The tensile stress leads to an increase of the electron mobility in the channel region.
摘要翻译： 半导体结构包括形成在衬底中的晶体管元件。 应力层形成在晶体管元件上。 应力层具有约900MPa以上的预定拉伸内应力。 由于这种高的固有应力，应力层对晶体管元件的沟道区域施加相当大的弹性力。 因此，在通道区域中产生拉伸应力。 拉伸应力导致通道区域中电子迁移率的增加。
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10.发明申请CONTACT OPTIMIZATION FOR ENHANCING STRESS TRANSFER IN CLOSELY SPACED TRANSISTORS 有权联系优化用于增强闭环间隔晶体管中的应力传递公开(公告)号：US20100327367A1
公开(公告)日：2010-12-30
申请号：US12823438
申请日：2010-06-25
申请人： Ralf Richter , Kai Frohberg , Holger Schuehrer
发明人： Ralf Richter , Kai Frohberg , Holger Schuehrer
IPC分类号： H01L27/092
CPC分类号： H01L23/485 , H01L21/76816 , H01L21/823412 , H01L21/823425 , H01L21/823475 , H01L21/84 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： By appropriately designing the geometric configuration of a contact level of a sophisticated semiconductor device, the tensile stress level of contact elements in N-channel transistors may be increased, while the tensile strain component of contact elements caused in the P-channel transistor may be reduced.
摘要翻译： 通过适当地设计复杂半导体器件的接触电平的几何形状，可以增加N沟道晶体管中的接触元件的拉伸应力水平，同时在P沟道晶体管中引起的接触元件的拉伸应变分量可能减小 。
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