公开(公告)号：US20050263897A1

公开(公告)日：2005-12-01

申请号：US11182929

申请日：2005-07-15

申请人： Kaiping Liu ,  Zhiqiang Wu ,  Jihong Chen

发明人： Kaiping Liu ,  Zhiqiang Wu ,  Jihong Chen

IPC分类号： H01L21/00 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/44 ,  H01L21/461 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/49

CPC分类号： H01L21/28035 ,  H01L29/4916

摘要： A method of forming a semiconductor device includes implanting a precipitate into a gate conductor of an at least partially formed semiconductor device. The gate conductor including a plurality of semiconductor grains. The boundaries of adjacent grains forming a dopant migration path. A plurality of precipitate regions are formed within the gate conductor. At least some of the precipitate regions located at a junction of at least two grains. The gate conductor of the at least partially formed semiconductor device is doped with a dopant. The dopant diffuses inwardly along the dopant migration path.

公开(公告)号：US07129582B2

公开(公告)日：2006-10-31

申请号：US11182929

申请日：2005-07-15

申请人： Kaiping Liu ,  Zhiqiang Wu ,  Jihong Chen

发明人： Kaiping Liu ,  Zhiqiang Wu ,  Jihong Chen

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/28035 ,  H01L29/4916

摘要： A method of forming a semiconductor device includes implanting a precipitate into a gate conductor of an at least partially formed semiconductor device. The gate conductor including a plurality of semiconductor grains. The boundaries of adjacent grains forming a dopant migration path. A plurality of precipitate regions are formed within the gate conductor. At least some of the precipitate regions located at a junction of at least two grains. The gate conductor of the at least partially formed semiconductor device is doped with a dopant. The dopant diffuses inwardly along the dopant migration path.

摘要翻译： 形成半导体器件的方法包括将沉淀注入到至少部分形成的半导体器件的栅极导体中。 栅极导体包括多个半导体晶粒。 形成掺杂剂迁移路径的相邻晶粒的边界。 在栅极导体内形成多个沉淀区。 位于至少两个晶粒的结的至少一些沉淀区域。 至少部分形成的半导体器件的栅极导体掺杂有掺杂剂。 掺杂剂沿掺杂剂迁移路径向内扩散。

公开(公告)号：US06913980B2

公开(公告)日：2005-07-05

申请号：US10609823

申请日：2003-06-30

申请人： Zhiqiang Wu ,  Jihong Chen ,  Kaiping Liu

发明人： Zhiqiang Wu ,  Jihong Chen ,  Kaiping Liu

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L29/66598 ,  H01L21/2652 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming an associated transistor is presented whereby short channel effects and junction capacitances are mitigated and enhanced switching speeds are thereby facilitated. Compensation regions are formed within a substrate by implanting dopants relatively deeply over source and drain regions formed within the substrate. The compensation regions are spaced apart slightly less than are the source and drain regions. This spacing affects potential contours and reduces junction capacitances within the transistor. The different distances between the source and drain regions and the compensation regions are achieved by forming and selectively adjusting sidewall spacers adjacent to a gate structure of the transistor. These spacers serve as guides for the dopants implanted into the substrate to form the source and drain regions and the compensation regions.

摘要翻译： 提出了一种形成相关晶体管的方法，从而减轻了短沟道效应和结电容，从而促进了切换速度的提高。 通过在衬底内形成的源区和漏区相对深地注入掺杂剂，在衬底内形成补偿区。 补偿区域比源极和漏极区域稍微间隔开。 该间隔影响电位轮廓并降低晶体管内的结电容。 通过形成和选择性地调节与晶体管的栅极结构相邻的侧壁间隔来实现源极和漏极区域与补偿区域之间的不同距离。 这些间隔物用作植入衬底中的掺杂剂以形成源区和漏区以及补偿区的引导。

公开(公告)号：US06955980B2

公开(公告)日：2005-10-18

申请号：US10233354

申请日：2002-08-30

申请人： Kaiping Liu ,  Zhiqiang Wu ,  Jihong Chen

发明人： Kaiping Liu ,  Zhiqiang Wu ,  Jihong Chen

IPC分类号： H01L21/00 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/44 ,  H01L21/461 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/49

CPC分类号： H01L21/28035 ,  H01L29/4916

摘要： A method of forming a semiconductor device includes implanting a precipitate into a gate conductor of an at least partially formed semiconductor device. The gate conductor including a plurality of semiconductor grains. The boundaries of adjacent grains forming a dopant migration path. A plurality of precipitate regions are formed within the gate conductor. At least some of the precipitate regions located at a junction of at least two grains. The gate conductor of the at least partially formed semiconductor device is doped with a dopant. The dopant diffuses inwardly along the dopant migration path.

摘要翻译： 形成半导体器件的方法包括将沉淀注入到至少部分形成的半导体器件的栅极导体中。 栅极导体包括多个半导体晶粒。 形成掺杂剂迁移路径的相邻晶粒的边界。 在栅极导体内形成多个沉淀区。 位于至少两个晶粒的结的至少一些沉淀区域。 至少部分形成的半导体器件的栅极导体掺杂有掺杂剂。 掺杂剂沿掺杂剂迁移路径向内扩散。

公开(公告)号：US06940137B2

公开(公告)日：2005-09-06

申请号：US10667012

申请日：2003-09-19

申请人： Jihong Chen ,  Zhiqiang Wu ,  Kaiping Liu

发明人： Jihong Chen ,  Zhiqiang Wu ,  Kaiping Liu

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L29/72

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/7833

摘要： The present invention provides a semiconductor device 200 having an angled compensation implant, a method of manufacture therefore and a method of manufacturing an integrated circuit including the angled compensation implant. In one embodiment, the method of manufacturing the semiconductor device 200 includes creating a halo implant 240 in a substrate 210, introducing a compensation implant 260 in the substrate 210 at an angle abnormal to the substrate 210 and forming a source/drain region 250 above the compensation implant 260, the angle reducing a capacitance associated with the halo implant 240 or the source/drain region 250. The method further includes placing a gate structure 230 over the substrate 210.

摘要翻译： 本发明提供一种具有成角度的补偿植入物的半导体器件200，因此制造方法以及制造包括角度补偿植入物的集成电路的方法。 在一个实施例中，制造半导体器件200的方法包括在衬底210中形成晕环植入物240，将衬底210中的补偿注入260以与衬底210成异角的方式引入补偿注入260，并在衬底210上方形成源/漏区250 补偿注入260，减小与晕轮植入物240或源极/漏极区域250相关联的电容的角度。 该方法还包括将栅极结构230放置在衬底210上。

公开(公告)号：US20050062103A1

公开(公告)日：2005-03-24

申请号：US10667012

申请日：2003-09-19

申请人： Jihong Chen ,  Zhiqiang Wu ,  Kaiping Liu

发明人： Jihong Chen ,  Zhiqiang Wu ,  Kaiping Liu

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/7833

摘要： The present invention provides a semiconductor device 200 having an angled compensation implant, a method of manufacture therefore and a method of manufacturing an integrated circuit including the angled compensation implant. In one embodiment, the method of manufacturing the semiconductor device 200 includes creating a halo implant 240 in a substrate 210, introducing a compensation implant 260 in the substrate 210 at an angle abnormal to the substrate 210 and forming a source/drain region 250 above the compensation implant 260, the angle reducing a capacitance associated with the halo implant 240 or the source/drain region 250. The method further includes placing a gate structure 230 over the substrate 210.

摘要翻译： 本发明提供一种具有成角度的补偿植入物的半导体器件200，因此制造方法以及制造包括角度补偿植入物的集成电路的方法。 在一个实施例中，制造半导体器件200的方法包括在衬底210中形成晕环植入物240，将衬底210中的补偿注入260以与衬底210成异角的方式引入补偿注入260，并在衬底210上方形成源/漏区250 补偿注入260，该角度减小与晕轮植入物240或源极/漏极区域250相关联的电容。该方法还包括将栅极结构230放置在衬底210上方。

公开(公告)号：US20050212041A1

公开(公告)日：2005-09-29

申请号：US11127941

申请日：2005-05-11

申请人： Zhiqiang Wu ,  Jihong Chen ,  Kaiping Liu

发明人： Zhiqiang Wu ,  Jihong Chen ,  Kaiping Liu

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L21/2652 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66598 ,  H01L29/7833

摘要： A method of forming an associated transistor is presented whereby short channel effects and junction capacitances are mitigated and enhanced switching speeds are thereby facilitated. Compensation regions are formed within a substrate by implanting dopants relatively deeply over source and drain regions formed within the substrate. The compensation regions are spaced apart slightly less than are the source and drain regions. This spacing affects potential contours and reduces junction capacitances within the transistor. The different distances between the source and drain regions and the compensation regions are achieved by forming and selectively adjusting sidewall spacers adjacent to a gate structure of the transistor. These spacers serve as guides for the dopants implanted into the substrate to form the source and drain regions and the compensation regions.

摘要翻译： 提出了一种形成相关晶体管的方法，从而减轻了短沟道效应和结电容，从而促进了切换速度的提高。 通过在衬底内形成的源区和漏区相对深地注入掺杂剂，在衬底内形成补偿区。 补偿区域比源极和漏极区域稍微间隔开。 该间隔影响电位轮廓并降低晶体管内的结电容。 通过形成和选择性地调节与晶体管的栅极结构相邻的侧壁间隔来实现源极和漏极区域与补偿区域之间的不同距离。 这些间隔物用作植入衬底中的掺杂剂以形成源区和漏区以及补偿区的引导。

公开(公告)号：US07118979B2

公开(公告)日：2006-10-10

申请号：US10701818

申请日：2003-11-05

申请人： Kaiping Liu ,  Zhiqiang Wu ,  Majid Movahed Mansoorz

发明人： Kaiping Liu ,  Zhiqiang Wu ,  Majid Movahed Mansoorz

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/4983 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2807 ,  H01L21/28105 ,  H01L21/823828

摘要： The present invention provides a transistor 100 having a germanium implant region 170 located therein, a method of manufacture therefor, and an integrated circuit including the aforementioned transistor. The transistor 100, in one embodiment, includes a polysilicon gate electrode 140 located over a semiconductor substrate 110, wherein a sidewall of the polysilicon gate electrode 140 has a germanium implanted region 170 located therein. The transistor 100 further includes source/drain regions 160 located within the semiconductor substrate 110 proximate the polysilicon gate electrode 140.

摘要翻译： 本发明提供一种具有位于其中的锗注入区域170的晶体管100及其制造方法，以及包括上述晶体管的集成电路。 在一个实施例中，晶体管100包括位于半导体衬底110上方的多晶硅栅电极140，其中多晶硅栅电极140的侧壁上具有锗注入区170。 晶体管100还包括靠近多晶硅栅电极140位于半导体衬底110内的源/漏区160。

公开(公告)号：US06727131B2

公开(公告)日：2004-04-27

申请号：US10279650

申请日：2002-10-24

申请人： Zhiqiang Wu ,  Kaiping Liu

发明人： Zhiqiang Wu ,  Kaiping Liu

IPC分类号： H01L218238

CPC分类号： H01L21/26513 ,  H01L21/324 ,  H01L29/6659

摘要： A method of forming a semiconductor device is provided that comprises forming a gate conductor proximate to and insulated from an outer surface of a semiconductor substrate. The gate conductor defines a channel region disposed inwardly from the gate conductor. Source and drain regions are formed in the semiconductor substrate, each disposed adjacent one edge of the channel region. The semiconductor substrate and the source and drain regions have an associated bottom wall junction capacitance. A transient enhanced diffusion anneal is used to affect ion concentration profiles associated with the source and drain regions, resulting in an increased balance in the ion concentration profiles of the source and drain regions and an ion concentration associated with the semiconductor substrate, which results in reduction of the bottom wall junction capacitance.

摘要翻译： 提供一种形成半导体器件的方法，其包括形成靠近并与半导体衬底的外表面绝缘的栅极导体。 栅极导体限定了从栅极导体向内设置的沟道区。 源极和漏极区域形成在半导体衬底中，每个设置在沟道区域的一个边缘附近。 半导体衬底和源极和漏极区域具有相关联的底壁结电容。 使用瞬时增强扩散退火来影响与源区和漏区相关的离子浓度分布，导致源区和漏区的离子浓度分布的增加平衡以及与半导体衬底相关联的离子浓度，这导致减少 的底壁结电容。

公开(公告)号：US07691714B2

公开(公告)日：2010-04-06

申请号：US11042415

申请日：2005-01-25

申请人： Antonio Luis Pacheco Rotondaro ,  Kaiping Liu ,  Jihong Chen ,  Amitabh Jain

发明人： Antonio Luis Pacheco Rotondaro ,  Kaiping Liu ,  Jihong Chen ,  Amitabh Jain

IPC分类号： H01L21/336 ,  H01L21/337

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/823814 ,  H01L21/823871

摘要： The present invention provides a method for manufacturing a transistor device, a method for manufacturing an integrated circuit, and a transistor device. The method for manufacturing the transistor device, among other steps, includes forming a gate structure over a substrate and forming source/drain regions in the substrate proximate the gate structure, the source/drain regions having a boundary that forms an electrical junction with the substrate. The method further includes forming dislocation loops in the substrate, the dislocation loops not extending outside the boundary of the source/drain regions.

摘要翻译： 本发明提供了晶体管器件的制造方法，集成电路的制造方法以及晶体管器件。 制造晶体管器件的方法以及其他步骤包括在衬底上形成栅极结构，并在栅极结构附近形成衬底中的源极/漏极区域，源极/漏极区域具有与衬底形成电连接的边界 。 该方法还包括在衬底中形成位错环，位错环不延伸到源/漏区的边界之外。