公开(公告)号：US06589871B2

公开(公告)日：2003-07-08

申请号：US09941757

申请日：2001-08-30

申请人： Yoshio Kawamura ,  Souichi Katagiri ,  Kan Yasui ,  Masayuki Nagasawa ,  Ui Yamaguchi

发明人： Yoshio Kawamura ,  Souichi Katagiri ,  Kan Yasui ,  Masayuki Nagasawa ,  Ui Yamaguchi

IPC分类号： H01L21302

CPC分类号： H01L22/20

摘要： A processing method capable of presenting the processing condition with a high accuracy to improve the productivity, including a step of applying a first processing to a first substrate and a step of applying a second processing to the first substrate or the second processing to a second substrate and determining a correlation function for each of in-plane positions as the data for the difference in a plurality of processing steps to each of the in-plane positions in view of on the in-plain distribution data to the in-plane position of each of the substrate as a result of the plurality of processings, calculating the in-plain distribution characteristics of the substrate under a desired processing condition in view of the correlation function and processing the substrate based on the in-plain distribution characteristics.

摘要翻译： 一种处理方法，其能够高精度地呈现处理条件以提高生产率，包括对第一基板施加第一处理的步骤和对第一基板施加第二处理的步骤或第二处理的步骤 以及将每个平面内位置的相关函数确定为多个处理步骤中的差数据的数据，以便在每个平面内位置中考虑到不均匀分布数据到每个平面内位置的平面内位置 作为多个处理的结果，考虑到相关函数，在所需的处理条件下计算衬底的不均匀分布特性，并且基于平原分布特性来处理衬底。

公开(公告)号：US06777337B2

公开(公告)日：2004-08-17

申请号：US09910904

申请日：2001-07-24

申请人： Kan Yasui ,  Souichi Katagiri ,  Masayuki Nagasawa ,  Ui Yamaguchi ,  Yoshio Kawamura

发明人： Kan Yasui ,  Souichi Katagiri ,  Masayuki Nagasawa ,  Ui Yamaguchi ,  Yoshio Kawamura

IPC分类号： H01L21302

CPC分类号： B24B37/042 ,  H01L21/31053

摘要： In a production process of a semiconductor device, planarizing of a wafer surface pattern can be performed to attain high planarity, good uniformity in the removal amount and improved controllability. This process include a step of planarizing a semiconductor wafer, from which at least two different films have been exposed, by polishing with a grindstone and a dispersant-containing processing liquid.

摘要翻译： 在半导体装置的制造方法中，可以进行晶片表面图案的平坦化，以获得高的平坦度，良好的去除量均匀性和改进的可控性。 该方法包括通过用磨石和含分散剂处理液进行抛光来平坦化半导体晶片的步骤，从半导体晶片至少暴露出两个不同的膜。

公开(公告)号：US06663468B2

公开(公告)日：2003-12-16

申请号：US09754193

申请日：2001-01-05

申请人： Yoshio Kawamura ,  Kan Yasui ,  Masahiko Sato ,  Souichi Katagiri ,  Masayuki Nagasawa ,  Kunio Harada ,  Satoshi Osabe ,  Ui Yamaguchi

发明人： Yoshio Kawamura ,  Kan Yasui ,  Masahiko Sato ,  Souichi Katagiri ,  Masayuki Nagasawa ,  Kunio Harada ,  Satoshi Osabe ,  Ui Yamaguchi

IPC分类号： B24B100

CPC分类号： B24B37/32 ,  H01L21/31053 ,  H01L21/3212

摘要： The problem of non-uniform polishing properties of a circumferential surface area of a substrate, so-called edge sagging phenomenon, is solved. When a thin film formed on a top surface of the substrate is polished while holding a back surface of the substrate, local stress at a circumferential end of the substrate is reduced by a guide installed so as to surround the substrate. Also, a deformation of the outer circumferential end portion of the substrate is reduced by a recessed groove provided on the guide. Since a thin film formed on the surface can be polished to be flat throughout the surface of the substrate without an occurrence of non-uniform polishing properties of the outer circumferential surface area of the substrate, so-called edge sagging phenomenon, a high-performance semiconductor device can be manufactured at a high yield and low costs.

摘要翻译： 解决了基板的圆周表面积的不均匀抛光性能，所谓的边缘下垂现象的问题。 当在保持基板的后表面的同时抛光形成在基板的顶表面上的薄膜时，通过安装成围绕基板的引导件来减小基板周向端部的局部应力。 此外，通过设置在引导件上的凹槽来减小基板的外周端部的变形。 由于形成在表面上的薄膜可以在基板的整个表面上被抛光成平坦的，而不会发生基板的外周表面积的不均匀的抛光性能，所谓的边缘下垂现象，高性能 可以以高产率和低成本制造半导体器件。

公开(公告)号：US06565424B2

公开(公告)日：2003-05-20

申请号：US09863264

申请日：2001-05-24

申请人： Souichi Katagiri ,  Yoshio Kawamura ,  Kan Yasui ,  Masayuki Nagasawa ,  Ui Yamaguchi

发明人： Souichi Katagiri ,  Yoshio Kawamura ,  Kan Yasui ,  Masayuki Nagasawa ,  Ui Yamaguchi

IPC分类号： B24B100

CPC分类号： B24B37/30 ,  B24B37/042 ,  B24B37/32

摘要： The invention provides a process apparatus including a wafer holder, and a process method, in which high planarization performance, scratch free process, narrow edge exclusion and high uniformity can be maintained for more than 10,000 processed wafers. The invention is achieved by providing a unit for keeping a retainer and surface of a polishing wheel non-contact with each other and controlling the gap within a certain range and by setting compression strength of the retainer at more than 3,000 kg/cm2.

公开(公告)号：US06734103B2

公开(公告)日：2004-05-11

申请号：US10081212

申请日：2002-02-25

申请人： Souichi Katagiri ,  Ui Yamaguchi ,  Seiichi Kondo ,  Kan Yasui ,  Yoshio Kawamura

发明人： Souichi Katagiri ,  Ui Yamaguchi ,  Seiichi Kondo ,  Kan Yasui ,  Yoshio Kawamura

IPC分类号： H01L21302

CPC分类号： B24B7/228 ,  B24B53/02 ,  C23F3/00 ,  H01L21/3212 ,  H01L21/7684

摘要： A method of manufacturing is described wherein a semiconductor device has a substrate as workpiece with an insulation film formed on the substrate, openings formed inside the insulation film, a first conductive film is formed inside the openings and on a surface of the insulation film, a second conductive film is formed on the first conductive film, and the first and the second conductive films are formed inside openings by planarizing a surface of second conductive film and a surface part of the first conductive film with a fixed abrasive tool. The method includes supplying a first processing liquid, planarizing the surface of the second conductive film with the first processing liquid and the fixed abrasive tool, switching the supply of liquid from a first processing liquid to a second processing liquid, and planarizing the surface of second conductive film and the surface of part of the first conductive film with the second processing liquid and the fixed abrasive tool.

摘要翻译： 描述了一种制造方法，其中半导体器件具有作为工件的基板，在基板上形成绝缘膜，形成在绝缘膜内部的开口，第一导电膜形成在开口内部和绝缘膜的表面上， 第二导电膜形成在第一导电膜上，并且通过用固定的研磨工具平面化第二导电膜的表面和第一导电膜的表面部分，在开口内形成第一和第二导电膜。 该方法包括提供第一处理液体，将第二导电膜的表面与第一处理液体和固定研磨工具平坦化，将液体从第一处理液体切换到第二处理液体，并将第二处理液体的表面平坦化 导电膜和第一导电膜的部分表面与第二处理液和固定研磨工具。

公开(公告)号：US07144298B2

公开(公告)日：2006-12-05

申请号：US11133300

申请日：2005-05-20

申请人： Souichi Katagiri ,  Ui Yamaguchi

发明人： Souichi Katagiri ,  Ui Yamaguchi

IPC分类号： B24B49/00

CPC分类号： B23H5/08 ,  B24B37/04 ,  C25F3/14 ,  C25F7/00 ,  H01L21/32125 ,  H01L21/7684

摘要： The object of the invention is to provide a method of manufacturing a semiconductor device and a processing apparatus for planarization wherein to form copper wiring in multiple layers. The removal of a residue of polishing by local electro polishing, the enhancement of the performance of planarization by using a grindstone and the reduction by small frictional force in electro polishing of damage, are enabled. To achieve the object, the following measures are taken. A residue of polishing of copper is removed by combining the detection of a local area including the residue of polishing of copper and local processing for electro polishing. As small-load processing for planarization is enabled by using electro polishing, multilayer interconnection structure using low-k material as a dielectric interlayer is also enabled. Plural pairs of small unit electrodes in a pair of which minus electrodes surround a plus electrode are provided to a tool for electro polishing, each electrode is connected to a power supply, pulse voltage is applied to each electrode and copper is electrolytically polished.

摘要翻译： 本发明的目的是提供一种制造半导体器件的方法和用于平坦化的处理装置，其中以多层形成铜布线。 通过局部电抛光去除抛光残留物，通过使用磨石提高平面化性能以及通过小摩擦力在电抛光中减少损伤。 为达到此目的，采取以下措施。 通过组合检测包括铜的抛光残余物和局部电抛光的局部区域来去除铜的抛光残余物。 通过使用电抛光能够实现平面化的小负载处理，也可以使用低k材料作为电介质中间层的多层互连结构。 将一对负电极围绕正电极的多对小单元电极提供给用于电抛光的工具，每个电极连接到电源，脉冲电压施加到每个电极并且铜被电解抛光。

公开(公告)号：US06908860B2

公开(公告)日：2005-06-21

申请号：US10457369

申请日：2003-06-10

申请人： Souichi Katagiri ,  Ui Yamaguchi

发明人： Souichi Katagiri ,  Ui Yamaguchi

IPC分类号： B23H5/08 ,  B24B37/04 ,  C25F3/14 ,  C25F7/00 ,  H01L21/304 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/768 ,  H01L21/302

CPC分类号： B23H5/08 ,  B24B37/04 ,  C25F3/14 ,  C25F7/00 ,  H01L21/32125 ,  H01L21/7684

摘要： The object of the invention is to provide a method of manufacturing a semiconductor device and a processing apparatus for planarization wherein to form copper wiring in multiple layers. The removal of a residue of polishing by local electro polishing, the enhancement of the performance of planarization by using a grindstone and the reduction by small frictional force in electro polishing of damage, are enabled. To achieve the object, the following measures are taken. A residue of polishing of copper is removed by combining the detection of a local area including the residue of polishing of copper and local processing for electro polishing. As small-load processing for planarization is enabled by using electro polishing, multilayer interconnection structure using low-k material as a dielectric interlayer is also enabled. Plural pairs of small unit electrodes in a pair of which minus electrodes surround a plus electrode are provided to a tool for electro polishing, each electrode is connected to a power supply, pulse voltage is applied to each electrode and copper is electrolytically polished.

公开(公告)号：US20050221608A1

公开(公告)日：2005-10-06

申请号：US11133300

申请日：2005-05-20

申请人： Souichi Katagiri ,  Ui Yamaguchi

发明人： Souichi Katagiri ,  Ui Yamaguchi

IPC分类号： B23H5/08 ,  B24B37/04 ,  C25F3/14 ,  C25F7/00 ,  H01L21/304 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/768 ,  H01L21/4763

CPC分类号： B23H5/08 ,  B24B37/04 ,  C25F3/14 ,  C25F7/00 ,  H01L21/32125 ,  H01L21/7684

摘要： The object of the invention is to provide a method of manufacturing a semiconductor device and a processing apparatus for planarization wherein to form copper wiring in multiple layers. The removal of a residue of polishing by local electro polishing, the enhancement of the performance of planarization by using a grindstone and the reduction by small frictional force in electro polishing of damage, are enabled. To achieve the object, the following measures are taken. A residue of polishing of copper is removed by combining the detection of a local area including the residue of polishing of copper and local processing for electro polishing. As small-load processing for planarization is enabled by using electro polishing, multilayer interconnection structure using low-k material as a dielectric interlayer is also enabled. Plural pairs of small unit electrodes in a pair of which minus electrodes surround a plus electrode are provided to a tool for electro polishing, each electrode is connected to a power supply, pulse voltage is applied to each electrode and copper is electrolytically polished.

摘要翻译： 本发明的目的是提供一种制造半导体器件的方法和用于平坦化的处理装置，其中以多层形成铜布线。 通过局部电抛光去除抛光残留物，通过使用磨石提高平面化性能以及通过小摩擦力在电抛光中减少损伤。 为达到此目的，采取以下措施。 通过组合检测包括铜的抛光残余物和局部电抛光的局部区域来去除铜的抛光残余物。 通过使用电抛光能够实现平面化的小负载处理，也可以使用低k材料作为电介质中间层的多层互连结构。 将一对负电极围绕正电极的多对小单元电极提供给用于电抛光的工具，每个电极连接到电源，脉冲电压施加到每个电极并且铜被电解抛光。

公开(公告)号：US06849542B2

公开(公告)日：2005-02-01

申请号：US10272831

申请日：2002-10-18

申请人： Soichi Katagiri ,  Ui Yamaguchi ,  Seiichi Kondo ,  Kan Yasui ,  Masahiro Kaise ,  Minoru Honda

发明人： Soichi Katagiri ,  Ui Yamaguchi ,  Seiichi Kondo ,  Kan Yasui ,  Masahiro Kaise ,  Minoru Honda

IPC分类号： B24B57/02 ,  B24D3/32 ,  B24D3/34 ,  B24D7/06 ,  H01L21/304 ,  H01L21/321 ,  H01L21/463

CPC分类号： B24B37/245 ,  B24B37/042 ,  B24B37/22 ,  B24B57/02 ,  B24D3/32 ,  B24D3/344 ,  B24D7/063 ,  H01L21/3212

摘要： The invention provides a method for manufacturing a semiconductor device with reduced dishing and erosion. In this method for manufacturing a semiconductor device, the convex/concave pattern is planarized by relatively moving a substrate having the convex/concave pattern on the surface and a polishing tool with pressing the convex/concave surface of the substrate on the polishing tool. The polishing tool is provided with a grindstone 10 having a plurality of polygonal segments 20, which comprises abrasive 23 that is bonded together with resin 24 and contains pores 22. The polygonal segments are arranged so that corners of three or more polygonal segments are not located near each other.

摘要翻译： 本发明提供一种制造具有减少的凹陷和侵蚀的半导体器件的方法。 在这种制造半导体器件的方法中，通过在表面上相对移动具有凸/凹图案的衬底和将抛光工具上的衬底的凸/凹表面压在一起的抛光工具，使凸/凹图案平坦化。 抛光工具设置有具有多个多边形节段20的磨石10，磨石10包括与树脂24结合并包含孔22的磨料23。多边形节段被布置成使得三个或更多个多边形节段的角部不位于 靠近对方

公开(公告)号：US09215089B2

公开(公告)日：2015-12-15

申请号：US13502078

申请日：2009-10-14

申请人： Masanori Muroyama ,  Masayoshi Esashi ,  Shuji Tanaka ,  Sakae Matsuzaki ,  Mitsutoshi Makihata ,  Yutaka Nonomura ,  Motohiro Fujiyoshi ,  Takahiro Nakayama ,  Ui Yamaguchi ,  Hitoshi Yamada

发明人： Masanori Muroyama ,  Masayoshi Esashi ,  Shuji Tanaka ,  Sakae Matsuzaki ,  Mitsutoshi Makihata ,  Yutaka Nonomura ,  Motohiro Fujiyoshi ,  Takahiro Nakayama ,  Ui Yamaguchi ,  Hitoshi Yamada

IPC分类号： G06F13/00 ,  H04L12/40 ,  G01L1/14 ,  G01L5/22 ,  G06F13/376

CPC分类号： H04L12/40032 ,  G01L1/142 ,  G01L1/146 ,  G01L5/228 ,  G06F13/376 ,  H04L12/40013

摘要： A touch sensor system includes buses, a plurality of touch sensor devices disposed on the buses, and an information integrating device that is connected to all the buses and integrates information from the touch sensor device. The touch sensor device includes a sensor unit and a signal processing unit that transmits a sensor data signal generated by processing an analog sensor signal to the information integrating device through the bus. The signal processing unit includes a digital converting unit, a threshold evaluating unit that gives a start permission of the signal process when a sensor value exceeds a preset threshold, an ID adding unit that adds a transmitter identification number to the sensor signal, and a data transmitting unit that outputs the sensor data signal to a signal line of the bus. Fast responses are made possible without increasing the amount of data and host processing load while including many touch sensor elements.

摘要翻译： 触摸传感器系统包括总线，布置在总线上的多个触摸传感器装置，以及连接到所有总线并且集成来自触摸传感器装置的信息的信息集成装置。 触摸传感器装置包括传感器单元和信号处理单元，该单元通过总线将通过处理模拟传感器信号而产生的传感器数据信号发送到信息集成装置。 信号处理单元包括：数字转换单元，当传感器值超过预设阈值时给出信号处理开始许可的阈值评估单元;将传感器信号加上发射机标识号的ID添加单元，以及数据 发送单元，其将传感器数据信号输出到总线的信号线。 快速响应是可能的，而不增加数据量和主机处理负载，同时包括许多触摸传感器元件。