公开(公告)号：US06734103B2

公开(公告)日：2004-05-11

申请号：US10081212

申请日：2002-02-25

申请人： Souichi Katagiri ,  Ui Yamaguchi ,  Seiichi Kondo ,  Kan Yasui ,  Yoshio Kawamura

发明人： Souichi Katagiri ,  Ui Yamaguchi ,  Seiichi Kondo ,  Kan Yasui ,  Yoshio Kawamura

IPC分类号： H01L21302

CPC分类号： B24B7/228 ,  B24B53/02 ,  C23F3/00 ,  H01L21/3212 ,  H01L21/7684

摘要： A method of manufacturing is described wherein a semiconductor device has a substrate as workpiece with an insulation film formed on the substrate, openings formed inside the insulation film, a first conductive film is formed inside the openings and on a surface of the insulation film, a second conductive film is formed on the first conductive film, and the first and the second conductive films are formed inside openings by planarizing a surface of second conductive film and a surface part of the first conductive film with a fixed abrasive tool. The method includes supplying a first processing liquid, planarizing the surface of the second conductive film with the first processing liquid and the fixed abrasive tool, switching the supply of liquid from a first processing liquid to a second processing liquid, and planarizing the surface of second conductive film and the surface of part of the first conductive film with the second processing liquid and the fixed abrasive tool.

摘要翻译： 描述了一种制造方法，其中半导体器件具有作为工件的基板，在基板上形成绝缘膜，形成在绝缘膜内部的开口，第一导电膜形成在开口内部和绝缘膜的表面上， 第二导电膜形成在第一导电膜上，并且通过用固定的研磨工具平面化第二导电膜的表面和第一导电膜的表面部分，在开口内形成第一和第二导电膜。 该方法包括提供第一处理液体，将第二导电膜的表面与第一处理液体和固定研磨工具平坦化，将液体从第一处理液体切换到第二处理液体，并将第二处理液体的表面平坦化 导电膜和第一导电膜的部分表面与第二处理液和固定研磨工具。

公开(公告)号：US06589871B2

公开(公告)日：2003-07-08

申请号：US09941757

申请日：2001-08-30

申请人： Yoshio Kawamura ,  Souichi Katagiri ,  Kan Yasui ,  Masayuki Nagasawa ,  Ui Yamaguchi

发明人： Yoshio Kawamura ,  Souichi Katagiri ,  Kan Yasui ,  Masayuki Nagasawa ,  Ui Yamaguchi

IPC分类号： H01L21302

CPC分类号： H01L22/20

摘要： A processing method capable of presenting the processing condition with a high accuracy to improve the productivity, including a step of applying a first processing to a first substrate and a step of applying a second processing to the first substrate or the second processing to a second substrate and determining a correlation function for each of in-plane positions as the data for the difference in a plurality of processing steps to each of the in-plane positions in view of on the in-plain distribution data to the in-plane position of each of the substrate as a result of the plurality of processings, calculating the in-plain distribution characteristics of the substrate under a desired processing condition in view of the correlation function and processing the substrate based on the in-plain distribution characteristics.

摘要翻译： 一种处理方法，其能够高精度地呈现处理条件以提高生产率，包括对第一基板施加第一处理的步骤和对第一基板施加第二处理的步骤或第二处理的步骤 以及将每个平面内位置的相关函数确定为多个处理步骤中的差数据的数据，以便在每个平面内位置中考虑到不均匀分布数据到每个平面内位置的平面内位置 作为多个处理的结果，考虑到相关函数，在所需的处理条件下计算衬底的不均匀分布特性，并且基于平原分布特性来处理衬底。

公开(公告)号：US06777337B2

公开(公告)日：2004-08-17

申请号：US09910904

申请日：2001-07-24

申请人： Kan Yasui ,  Souichi Katagiri ,  Masayuki Nagasawa ,  Ui Yamaguchi ,  Yoshio Kawamura

发明人： Kan Yasui ,  Souichi Katagiri ,  Masayuki Nagasawa ,  Ui Yamaguchi ,  Yoshio Kawamura

IPC分类号： H01L21302

CPC分类号： B24B37/042 ,  H01L21/31053

摘要： In a production process of a semiconductor device, planarizing of a wafer surface pattern can be performed to attain high planarity, good uniformity in the removal amount and improved controllability. This process include a step of planarizing a semiconductor wafer, from which at least two different films have been exposed, by polishing with a grindstone and a dispersant-containing processing liquid.

摘要翻译： 在半导体装置的制造方法中，可以进行晶片表面图案的平坦化，以获得高的平坦度，良好的去除量均匀性和改进的可控性。 该方法包括通过用磨石和含分散剂处理液进行抛光来平坦化半导体晶片的步骤，从半导体晶片至少暴露出两个不同的膜。

公开(公告)号：US06663468B2

公开(公告)日：2003-12-16

申请号：US09754193

申请日：2001-01-05

申请人： Yoshio Kawamura ,  Kan Yasui ,  Masahiko Sato ,  Souichi Katagiri ,  Masayuki Nagasawa ,  Kunio Harada ,  Satoshi Osabe ,  Ui Yamaguchi

发明人： Yoshio Kawamura ,  Kan Yasui ,  Masahiko Sato ,  Souichi Katagiri ,  Masayuki Nagasawa ,  Kunio Harada ,  Satoshi Osabe ,  Ui Yamaguchi

IPC分类号： B24B100

CPC分类号： B24B37/32 ,  H01L21/31053 ,  H01L21/3212

摘要： The problem of non-uniform polishing properties of a circumferential surface area of a substrate, so-called edge sagging phenomenon, is solved. When a thin film formed on a top surface of the substrate is polished while holding a back surface of the substrate, local stress at a circumferential end of the substrate is reduced by a guide installed so as to surround the substrate. Also, a deformation of the outer circumferential end portion of the substrate is reduced by a recessed groove provided on the guide. Since a thin film formed on the surface can be polished to be flat throughout the surface of the substrate without an occurrence of non-uniform polishing properties of the outer circumferential surface area of the substrate, so-called edge sagging phenomenon, a high-performance semiconductor device can be manufactured at a high yield and low costs.

摘要翻译： 解决了基板的圆周表面积的不均匀抛光性能，所谓的边缘下垂现象的问题。 当在保持基板的后表面的同时抛光形成在基板的顶表面上的薄膜时，通过安装成围绕基板的引导件来减小基板周向端部的局部应力。 此外，通过设置在引导件上的凹槽来减小基板的外周端部的变形。 由于形成在表面上的薄膜可以在基板的整个表面上被抛光成平坦的，而不会发生基板的外周表面积的不均匀的抛光性能，所谓的边缘下垂现象，高性能 可以以高产率和低成本制造半导体器件。

公开(公告)号：US06565424B2

公开(公告)日：2003-05-20

申请号：US09863264

申请日：2001-05-24

申请人： Souichi Katagiri ,  Yoshio Kawamura ,  Kan Yasui ,  Masayuki Nagasawa ,  Ui Yamaguchi

发明人： Souichi Katagiri ,  Yoshio Kawamura ,  Kan Yasui ,  Masayuki Nagasawa ,  Ui Yamaguchi

IPC分类号： B24B100

CPC分类号： B24B37/30 ,  B24B37/042 ,  B24B37/32

摘要： The invention provides a process apparatus including a wafer holder, and a process method, in which high planarization performance, scratch free process, narrow edge exclusion and high uniformity can be maintained for more than 10,000 processed wafers. The invention is achieved by providing a unit for keeping a retainer and surface of a polishing wheel non-contact with each other and controlling the gap within a certain range and by setting compression strength of the retainer at more than 3,000 kg/cm2.

公开(公告)号：US06612912B2

公开(公告)日：2003-09-02

申请号：US09371003

申请日：1999-08-10

申请人： Kan Yasui ,  Souichi Katagiri ,  Shigeo Moriyama ,  Yoshio Kawamura ,  Ryousei Kawai ,  Sadayuki Nishimura ,  Masahiko Sato

发明人： Kan Yasui ,  Souichi Katagiri ,  Shigeo Moriyama ,  Yoshio Kawamura ,  Ryousei Kawai ,  Sadayuki Nishimura ,  Masahiko Sato

IPC分类号： B24B100

CPC分类号： B24B53/017 ,  B24B1/04 ,  B24B37/042 ,  B24B53/12

摘要： A method for fabricating a semiconductor device includes grindstone surface activation treatment by means of a brush or ultrasonic wave carried out when a concave/convex pattern of a semiconductor wafer is planarized by polishing a semiconductor wafer held by a wafer holder by using a grindstone constituted of abrasive grains and material for holding the abrasive grains onto which the semiconductor wafer is pressed with relative motion. The semiconductor wafer is processed with high removal rate and the polishing thickness is controlled accurately.

摘要翻译： 一种制造半导体器件的方法包括：当半导体晶片的凹凸图案通过使用由晶片保持器保持的半导体晶片进行平面化而进行的刷子或超声波的磨石表面激活处理， 磨料颗粒和用于保持磨料颗粒的材料，半导体晶片被相对运动地压在其上。 半导体晶片以高去除率进行处理，并且精确地控制抛光厚度。

公开(公告)号：US06723144B2

公开(公告)日：2004-04-20

申请号：US10308088

申请日：2002-12-03

申请人： Souichi Katagiri ,  Kan Yasui ,  Ryousei Kawai ,  Sadayuki Nishimura ,  Masahiko Sato ,  Yoshio Kawamura ,  Shigeo Moriyama

发明人： Souichi Katagiri ,  Kan Yasui ,  Ryousei Kawai ,  Sadayuki Nishimura ,  Masahiko Sato ,  Yoshio Kawamura ,  Shigeo Moriyama

IPC分类号： B24D302

CPC分类号： B24B37/245 ,  B24D3/32 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76819 ,  H01L21/7684

摘要： A film formed on a surface of a wafer on which an integrated circuit is to be constructed can be planarized by using a fixed abrasive tool regardless of the width of elements of a pattern underlying the film. The fixed abrasive tool is liable to form scratches in the surface of the film. A planarizing process of the present invention employs a fixed abrasive tool containing substances harder than the film to be planarized in a content of 10 ppm or below and having a mean pore diameter of 0.2 &mgr;m or below.

摘要翻译： 形成在其上将要构造集成电路的晶片的表面上的膜可以通过使用固定的研磨工具进行平面化，而与薄膜下面的图案的元件的宽度无关。 固定的研磨工具易于在膜表面形成划痕。 本发明的平面化方法使用含有比待平坦化的膜更硬的物质的固定研磨工具，其含量为10ppm以下，平均孔径为0.2μm以下。

公开(公告)号：US06524961B1

公开(公告)日：2003-02-25

申请号：US09359760

申请日：1999-07-22

申请人： Souichi Katagiri ,  Kan Yasui ,  Ryousei Kawai ,  Sadayuki Nishimura ,  Masahiko Sato ,  Yoshio Kawamura ,  Shigeo Moriyama

发明人： Souichi Katagiri ,  Kan Yasui ,  Ryousei Kawai ,  Sadayuki Nishimura ,  Masahiko Sato ,  Yoshio Kawamura ,  Shigeo Moriyama

IPC分类号： H01L21461

CPC分类号： B24B37/245 ,  B24D3/32 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76819 ,  H01L21/7684

摘要： A film formed on a surface of a wafer on which an integrated circuit is to be constructed can be planarized by using a fixed abrasive tool regardless of the width of elements of a pattern underlying the film. The fixed abrasive tool is liable to form scratches in the surface of the film. A planarizing process of the present invention employs a fixed abrasive tool containing substances harder than the film to be planarized in a content of 10 ppm or below and having a mean pore diameter of 0.2 &mgr;m or below.

公开(公告)号：US07062344B2

公开(公告)日：2006-06-13

申请号：US10713012

申请日：2003-11-17

申请人： Natsuki Yokoyama ,  Yoshifumi Kawamoto ,  Eiichi Murakami ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Yoshio Kawamura

发明人： Natsuki Yokoyama ,  Yoshifumi Kawamoto ,  Eiichi Murakami ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Yoshio Kawamura

IPC分类号： G06F19/00

CPC分类号： C23C14/568 ,  C23C16/54 ,  G05B19/41865 ,  G05B2219/45031 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67173 ,  H01L21/67184 ,  H01L21/67276 ,  H01L21/67727 ,  H01L21/67745 ,  Y02P90/14 ,  Y02P90/20 ,  Y02P90/28 ,  Y10S414/135 ,  Y10S414/137 ,  Y10S438/908 ,  Y10T29/41

摘要： Disclosed is a fabricating system including a plurality of processing apparatuses connected to each other by means of an inter-apparatus transporter, wherein one group of semiconductor wafers are processed in processing apparatuses and other group of wafers are transported to specified processing apparatuses for a time interval from (To+T) to a time To; and another group of wafers are processed and the remaining group of wafers are transported for a time interval from (To+T) to (To+2T). Since processing apparatuses can receive at least one of works from the inter-apparatus transporter for a time interval T min, the distribution of works from the transporter to processing apparatuses is completed for the time interval T min. The transporter is emptied for each time interval T min, and works are unloaded to the emptied transporter, which makes easy the scheduling, control and management of the transporting of a plurality of works in the fabricating system. Moreover, since the fabricating system including processing apparatuses is periodically controlled at a cycle time T min, the scheduling of a plurality of works can be made easy, to enhance the level of optimization, thus improving the productivity.

公开(公告)号：US5308757A

公开(公告)日：1994-05-03

申请号：US742419

申请日：1991-08-08

申请人： Yoshio Kawamura ,  Yoshu Yoshiba ,  Shinji Tanaka ,  Kazuo Sato ,  Jiro Kikuchi ,  Kahoru Takahashi

发明人： Yoshio Kawamura ,  Yoshu Yoshiba ,  Shinji Tanaka ,  Kazuo Sato ,  Jiro Kikuchi ,  Kahoru Takahashi

IPC分类号： C12M1/00 ,  C12M1/34 ,  C12M3/00 ,  C12N5/00 ,  C12N5/04 ,  C12Q1/06 ,  G01N33/487 ,  C12Q1/02 ,  C12M1/20

CPC分类号： C12M41/46 ,  C12Q1/06 ,  Y10S436/807 ,  Y10S436/809

摘要： In determining the effectiveness of parameters on cells, after treatment of the cells with one or more selected parameters, the results of the treatment can be quickly determined by measuring the number n.sub.0 of cells having a predetermined cell form, subsequently mechanically stressing the cells for a sufficient period of time t to change the cell form substantially, thereafter again measuring the number n of cells having the predetermined cell form, and determining the cell viability .tau.defined by .tau.=t/1n(n.sub.0 /n).

摘要翻译： 在确定细胞参数的有效性时，在用一个或多个所选参数处理细胞后，可以通过测量具有预定细胞形式的细胞的数目n0来快速确定治疗结果，随后将细胞机械胁迫 足够的时间t以基本上改变细胞形式，然后再次测量具有预定细胞形式的细胞的数目n，以及确定由tau = t / 1n（n0 / n）定义的细胞存活力τ。