公开(公告)号：US07537959B2

公开(公告)日：2009-05-26

申请号：US11889400

申请日：2007-08-13

申请人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

发明人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

IPC分类号： H01L21/00 ,  H01L21/26 ,  H01L21/44 ,  H01L29/40

CPC分类号： H01L25/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05569 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  Y02P80/30 ,  Y10S438/977 ,  Y10T436/104998 ,  Y10T436/108331 ,  Y10T436/17 ,  Y10T436/175383 ,  H01L2224/81 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.

摘要翻译： 通过在与芯片相邻的划线中形成连接通孔并且使用重新布线将连接器件芯片焊盘连接到连接通孔，在晶片级制造芯片堆叠封装。 然后将下部芯片连接并连接到可以是测试晶片的衬底，并且上部芯片被附接并连接到下部芯片，电连接通过它们各自的连接通孔来实现。 除了连接通孔之外，芯片堆叠封装可以包括在垂直相邻的芯片和/或下部芯片和衬底之间形成的连接凸块。 优选的基板是测试晶片，其允许附接的芯片被测试并且如果有故障则被替换，从而确保每层堆叠的芯片仅在连接下一层芯片之前仅包括“已知的芯片”，从而提高生产率 并提高产量。

公开(公告)号：US20070281374A1

公开(公告)日：2007-12-06

申请号：US11889400

申请日：2007-08-13

申请人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

发明人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

IPC分类号： H01L21/66 ,  H01L21/58

CPC分类号： H01L25/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05569 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  Y02P80/30 ,  Y10S438/977 ,  Y10T436/104998 ,  Y10T436/108331 ,  Y10T436/17 ,  Y10T436/175383 ,  H01L2224/81 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.

公开(公告)号：US20090209063A1

公开(公告)日：2009-08-20

申请号：US12385855

申请日：2009-04-22

申请人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-sik Chung

发明人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-sik Chung

IPC分类号： H01L21/50 ,  H01L21/768

CPC分类号： H01L25/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05569 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  Y02P80/30 ,  Y10S438/977 ,  Y10T436/104998 ,  Y10T436/108331 ,  Y10T436/17 ,  Y10T436/175383 ,  H01L2224/81 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for manufacturing chip stack packages may include: providing at least two wafers, each wafer having a plurality of chips, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes; forming connection vias by filling the via holes; establishing electrical connections between the chip pads and corresponding connection vias; removing material from the back sides of the wafers to form thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane; attaching a first plurality of individual chips to a test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures; encapsulating the plurality of chip stack structures; and separating the plurality of chip stack structures to form individual chip stack packages.

摘要翻译： 用于制造芯片堆叠封装的方法可以包括：提供至少两个晶片，每个晶片具有多个芯片，以及在相邻芯片之间形成并分隔相邻芯片的划线; 在划线的周边部分形成多个通孔; 通过填充通孔形成连接通孔; 建立芯片焊盘和相应的连接通孔之间的电连接; 从晶片的背面去除材料以形成薄的晶片; 通过去除每个划线的中心部分将薄的晶片分离成单独的芯片; 将第一多个独立芯片附接到测试晶片; 将第二多个独立芯片附接到所述第一多个独立芯片以形成多个芯片堆叠结构; 封装所述多个芯片堆叠结构; 以及分离所述多个芯片堆叠结构以形成单独的芯片堆叠封装。

公开(公告)号：US08368231B2

公开(公告)日：2013-02-05

申请号：US13154165

申请日：2011-06-06

申请人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

发明人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

IPC分类号： H01L23/48

CPC分类号： H01L25/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05569 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  Y02P80/30 ,  Y10S438/977 ,  Y10T436/104998 ,  Y10T436/108331 ,  Y10T436/17 ,  Y10T436/175383 ,  H01L2224/81 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for manufacturing chip stack packages may include: providing at least two wafers, each wafer having a plurality of chips, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes; forming connection vias by filling the via holes; establishing electrical connections between the chip pads and corresponding connection vias; removing material from the back sides of the wafers to form thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane; attaching a first plurality of individual chips to a test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures; encapsulating the plurality of chip stack structures; and separating the plurality of chip stack structures to form individual chip stack packages.

公开(公告)号：US20110237004A1

公开(公告)日：2011-09-29

申请号：US13154165

申请日：2011-06-06

申请人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

发明人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

IPC分类号： H01L21/66

CPC分类号： H01L25/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05569 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  Y02P80/30 ,  Y10S438/977 ,  Y10T436/104998 ,  Y10T436/108331 ,  Y10T436/17 ,  Y10T436/175383 ,  H01L2224/81 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for manufacturing chip stack packages may include: providing at least two wafers, each wafer having a plurality of chips, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes; forming connection vias by filling the via holes; establishing electrical connections between the chip pads and corresponding connection vias; removing material from the back sides of the wafers to form thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane; attaching a first plurality of individual chips to a test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures; encapsulating the plurality of chip stack structures; and separating the plurality of chip stack structures to form individual chip stack packages.

摘要翻译： 用于制造芯片堆叠封装的方法可以包括：提供至少两个晶片，每个晶片具有多个芯片，以及在相邻芯片之间形成并分隔相邻芯片的划线; 在划线的周边部分形成多个通孔; 通过填充通孔形成连接通孔; 建立芯片焊盘和相应的连接通孔之间的电连接; 从晶片的背面去除材料以形成薄的晶片; 通过去除每个划线的中心部分将薄的晶片分离成单独的芯片; 将第一多个独立芯片附接到测试晶片; 将第二多个独立芯片附接到所述第一多个独立芯片以形成多个芯片堆叠结构; 封装所述多个芯片堆叠结构; 以及分离所述多个芯片堆叠结构以形成单独的芯片堆叠封装。

公开(公告)号：US07977156B2

公开(公告)日：2011-07-12

申请号：US12385855

申请日：2009-04-22

申请人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

发明人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

IPC分类号： H01L21/00 ,  H01L21/26 ,  H01L21/44 ,  H01L29/40

CPC分类号： H01L25/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05569 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  Y02P80/30 ,  Y10S438/977 ,  Y10T436/104998 ,  Y10T436/108331 ,  Y10T436/17 ,  Y10T436/175383 ,  H01L2224/81 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for manufacturing chip stack packages may include: providing at least two wafers, each wafer having a plurality of chips, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes; forming connection vias by filling the via holes; establishing electrical connections between the chip pads and corresponding connection vias; removing material from the back sides of the wafers to form thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane; attaching a first plurality of individual chips to a test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures; encapsulating the plurality of chip stack structures; and separating the plurality of chip stack structures to form individual chip stack packages.

摘要翻译： 用于制造芯片堆叠封装的方法可以包括：提供至少两个晶片，每个晶片具有多个芯片，以及在相邻芯片之间形成并分隔相邻芯片的划线; 在划线的周边部分形成多个通孔; 通过填充通孔形成连接通孔; 建立芯片焊盘和相应的连接通孔之间的电连接; 从晶片的背面去除材料以形成薄的晶片; 通过去除每个划线的中心部分将薄的晶片分离成单独的芯片; 将第一多个独立芯片附接到测试晶片; 将第二多个独立芯片附接到所述第一多个独立芯片以形成多个芯片堆叠结构; 封装所述多个芯片堆叠结构; 以及分离所述多个芯片堆叠结构以形成单独的芯片堆叠封装。

公开(公告)号：US07276799B2

公开(公告)日：2007-10-02

申请号：US10890995

申请日：2004-07-15

申请人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

发明人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

IPC分类号： H01L23/48

CPC分类号： H01L25/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05569 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  Y02P80/30 ,  Y10S438/977 ,  Y10T436/104998 ,  Y10T436/108331 ,  Y10T436/17 ,  Y10T436/175383 ,  H01L2224/81 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.

摘要翻译： 通过在与芯片相邻的划线中形成连接通孔并且使用重新布线将连接器件芯片焊盘连接到连接通孔，在晶片级制造芯片堆叠封装。 然后将下部芯片连接并连接到可以是测试晶片的衬底，并且上部芯片被附接并连接到下部芯片，电连接通过它们各自的连接通孔来实现。 除了连接通孔之外，芯片堆叠封装可以包括在垂直相邻的芯片和/或下部芯片和衬底之间形成的连接凸块。 优选的基板是测试晶片，其允许附接的芯片被测试并且如果有故障则被替换，从而确保每层堆叠的芯片仅在连接下一层芯片之前仅包括“已知的芯片”，从而提高生产率 并提高产量。

公开(公告)号：US20050046002A1

公开(公告)日：2005-03-03

申请号：US10890995

申请日：2004-07-15

申请人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

发明人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/98 ,  H01L23/48 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L21/44 ,  H01L21/48 ,  H01L23/02

CPC分类号： H01L25/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05569 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  Y02P80/30 ,  Y10S438/977 ,  Y10T436/104998 ,  Y10T436/108331 ,  Y10T436/17 ,  Y10T436/175383 ,  H01L2224/81 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.

摘要翻译： 通过在与芯片相邻的划线中形成连接通孔并且使用重新布线将连接器件芯片焊盘连接到连接通孔，在晶片级制造芯片堆叠封装。 然后将下部芯片连接并连接到可以是测试晶片的衬底，并且上部芯片被附接并连接到下部芯片，电连接通过它们各自的连接通孔来实现。 除了连接通孔之外，芯片堆叠封装可以包括在垂直相邻的芯片和/或下部芯片和衬底之间形成的连接凸块。 优选的基板是测试晶片，其允许附接的芯片被测试并且如果有故障则被替换，从而确保每层堆叠的芯片仅在连接下一层芯片之前仅包括“已知的芯片”，从而提高生产率 并提高产量。

公开(公告)号：US07262475B2

公开(公告)日：2007-08-28

申请号：US11177335

申请日：2005-07-11

申请人： Yong-Chai Kwon ,  Kang-Wook Lee ,  Gu-Sung Kim ,  Seong-Il Han ,  Keum-Hee Ma ,  Suk-Chae Kang ,  Dong-Hyeon Jang

发明人： Yong-Chai Kwon ,  Kang-Wook Lee ,  Gu-Sung Kim ,  Seong-Il Han ,  Keum-Hee Ma ,  Suk-Chae Kang ,  Dong-Hyeon Jang

IPC分类号： H01L31/0203 ,  H01L23/495

CPC分类号： H01L27/14618 ,  H01L27/1464 ,  H01L27/14685 ,  H01L2224/48091 ,  H04N5/2257 ,  H01L2924/00014

摘要： An image sensor device including a protective plate may be manufactured from an image sensor chip having an active surface and a back surface opposite to the active surface. The image sensor chip may include chip pads formed in a peripheral region of the active surface, a microlens formed in a central region of the active surface and an intermediate region between the peripheral and central regions. A protective plate may be attached to the intermediate region of the active surface of the image sensor chip using an adhesive pattern that is sized and configured to maintain a separation distance between the protective plate and the microlens formed on the image sensor chip. Conductive plugs, formed before, during or after the manufacture of the image sensor chip circuitry may provide electrical connection between the chip pads and external connectors.

摘要翻译： 包括保护板的图像传感器装置可以由具有与活性表面相对的活性表面和背面的图像传感器芯片制造。 图像传感器芯片可以包括形成在有源表面的周边区域中的芯片焊盘，形成在有源表面的中心区域中的微透镜和在周边区域和中心区域之间的中间区域。 可以使用粘合剂图案将保护板附接到图像传感器芯片的有效表面的中间区域，该粘合剂图案的尺寸和构造用于保持保护板和形成在图像传感器芯片上的微透镜之间的间隔距离。 在图像传感器芯片电路制造之前，期间或之后形成的导电插塞可以提供芯片焊盘和外部连接器之间的电连接。

公开(公告)号：US07534656B2

公开(公告)日：2009-05-19

申请号：US11878220

申请日：2007-07-23

申请人： Yong-Chai Kwon ,  Kang-Wook Lee ,  Gu-Sung Kim ,  Seong-Il Han ,  Keum-Hee Ma ,  Suk-Chae Kang ,  Dong-Hyeon Jang

发明人： Yong-Chai Kwon ,  Kang-Wook Lee ,  Gu-Sung Kim ,  Seong-Il Han ,  Keum-Hee Ma ,  Suk-Chae Kang ,  Dong-Hyeon Jang

IPC分类号： H01L21/00 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/46 ,  H01L21/78 ,  H01L21/301

CPC分类号： H01L27/14618 ,  H01L27/1464 ,  H01L27/14685 ,  H01L2224/48091 ,  H04N5/2257 ,  H01L2924/00014

摘要： An image sensor device including a protective plate may be manufactured from an image sensor chip having an active surface and a back surface opposite to the active surface. The image sensor chip may include chip pads formed in a peripheral region of the active surface, a microlens formed in a central region of the active surface and an intermediate region between the peripheral and central regions. A protective plate may be attached to the intermediate region of the active surface of the image sensor chip using an adhesive pattern that is sized and configured to maintain a separation distance between the protective plate and the microlens formed on the image sensor chip. Conductive plugs, formed before, during or after the manufacture of the image sensor chip circuitry may provide electrical connection between the chip pads and external connectors.

摘要翻译： 包括保护板的图像传感器装置可以由具有与活性表面相对的活性表面和背面的图像传感器芯片制造。 图像传感器芯片可以包括形成在有源表面的周边区域中的芯片焊盘，形成在有源表面的中心区域中的微透镜和在周边区域和中心区域之间的中间区域。 可以使用粘合剂图案将保护板附接到图像传感器芯片的有效表面的中间区域，该粘合剂图案的尺寸和构造用于保持保护板和形成在图像传感器芯片上的微透镜之间的间隔距离。 在图像传感器芯片电路制造之前，期间或之后形成的导电插塞可以提供芯片焊盘和外部连接器之间的电连接。