LOW SERIES RESISTANCE TRANSISTOR STRUCTURE ON SILICON ON INSULATOR LAYER
    1.
    发明申请
    LOW SERIES RESISTANCE TRANSISTOR STRUCTURE ON SILICON ON INSULATOR LAYER 有权
    绝缘体层上硅的低串联电阻晶体管结构

    公开(公告)号:US20130175625A1

    公开(公告)日:2013-07-11

    申请号:US13622712

    申请日:2012-09-19

    IPC分类号: H01L29/78

    摘要: A transistor structure includes a channel located in an extremely thin silicon on insulator (ETSOI) layer and disposed between a raised source and a raised drain, a gate structure having a gate conductor disposed over the channel and between the source and the drain, and a gate spacer layer disposed over the gate conductor. The raised source and the raised drain each have a facet that is upwardly sloping away from the gate structure. A lower portion of the source and a lower portion of the drain are separated from the channel by an extension region containing a dopant species diffused from a dopant-containing glass.

    摘要翻译: 晶体管结构包括位于极薄的绝缘体上硅(ETSOI)层上的通道,并且设置在升高的源极和升高的漏极之间的栅极结构,栅极结构具有布置在沟道上方以及源极与漏极之间的栅极结构,以及 栅极间隔层设置在栅极导体上。 升高的源极和升高的漏极各自具有远离栅极结构向上倾斜的小面。 源极的下部和漏极的下部通过包含从含掺杂剂的玻璃扩散的掺杂​​物种的延伸区与沟道分离。

    Method to form low series resistance transistor devices on silicon on insulator layer
    2.
    发明授权
    Method to form low series resistance transistor devices on silicon on insulator layer 有权
    在绝缘体硅层上形成低串联电阻晶体管器件的方法

    公开(公告)号:US08440552B1

    公开(公告)日:2013-05-14

    申请号:US13346008

    申请日:2012-01-09

    IPC分类号: H01L21/225

    摘要: A method includes providing an ETSOI wafer having a semiconductor layer having a top surface with at least one gate structure having on sidewalls thereof a layer of dielectric material. A portion of the layer of dielectric material extends away from the gate structure on the surface of the semiconductor layer. The method further includes faulting a raised S/D on the semiconductor layer adjacent to the portion of the layer of dielectric material, removing the portion of the layer of dielectric material to expose an underlying portion of the surface of the semiconductor layer and applying a layer of glass containing a dopant to cover at least the exposed portion of the surface of the semiconductor layer. The method further includes diffusing the dopant through the exposed portion of the surface of the semiconductor layer to form a source extension region and a drain extension region.

    摘要翻译: 一种方法包括提供具有半导体层的ETSOI晶片,所述半导体层具有顶表面,所述半导体层具有至少一个在其侧壁上具有介电材料层的栅极结构。 电介质材料层的一部分远离半导体层表面上的栅极结构延伸。 该方法还包括将邻近该介电材料层的部分的半导体层上的升高的S / D断开,去除介电材料层的该部分以暴露该半导体层表面的下面部分并施加一层 的含有掺杂剂的玻璃以至少覆盖半导体层的表面的暴露部分。 该方法还包括通过半导体层的表面的暴露部分扩散掺杂剂以形成源极延伸区域和漏极延伸区域。

    ROBUST ISOLATION FOR THIN-BOX ETSOI MOSFETS
    3.
    发明申请
    ROBUST ISOLATION FOR THIN-BOX ETSOI MOSFETS 有权
    用于薄盒ETSOI MOSFET的稳定隔离

    公开(公告)号:US20130264641A1

    公开(公告)日:2013-10-10

    申请号:US13442168

    申请日:2012-04-09

    摘要: A thin BOX ETSOI device with robust isolation and method of manufacturing. The method includes providing a wafer with at least a pad layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less. The process continues with etching a shallow trench into the wafer, extending partially into the second semiconductor layer and forming first spacers on the sidewalls of said shallow trench. After spacer formation, the process continues by etching an area directly below and between the first spacers, exposing the underside of the first spacers, forming second spacers covering all exposed portions of the first spacers, wherein the pad oxide layer is removed, and forming a gate structure over the first semiconductor wafer.

    摘要翻译: 薄型BOX ETSOI器件,具有强大的隔离性和制造方法。 该方法包括提供晶片至少一覆盖在覆盖第二半导体层的氧化物层上的第一半导体层的焊盘层,其中第一半导体层具有10nm或更小的厚度。 该过程继续蚀刻到晶片中的浅沟槽,部分地延伸到第二半导体层中并且在所述浅沟槽的侧壁上形成第一间隔物。 在间隔物形成之后,该过程继续蚀刻直接在第一间隔物下面和之间的区域,暴露第一间隔物的下侧,形成覆盖第一间隔物的所有暴露部分的第二间隔区,其中除去氧化垫层, 第一半导体晶片上的栅极结构。

    Robust isolation for thin-box ETSOI MOSFETS
    4.
    发明授权
    Robust isolation for thin-box ETSOI MOSFETS 有权
    薄型ETSOI MOSFET的强大隔离性

    公开(公告)号:US08927387B2

    公开(公告)日:2015-01-06

    申请号:US13442168

    申请日:2012-04-09

    摘要: A thin BOX ETSOI device with robust isolation and method of manufacturing. The method includes providing a wafer with at least a pad layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less. The process continues with etching a shallow trench into the wafer, extending partially into the second semiconductor layer and forming first spacers on the sidewalls of said shallow trench. After spacer formation, the process continues by etching an area directly below and between the first spacers, exposing the underside of the first spacers, forming second spacers covering all exposed portions of the first spacers, wherein the pad oxide layer is removed, and forming a gate structure over the first semiconductor wafer.

    摘要翻译: 薄型BOX ETSOI器件,具有强大的隔离性和制造方法。 该方法包括提供晶片至少一覆盖在覆盖第二半导体层的氧化物层上的第一半导体层的焊盘层,其中第一半导体层具有10nm或更小的厚度。 该过程继续蚀刻到晶片中的浅沟槽,部分地延伸到第二半导体层中并且在所述浅沟槽的侧壁上形成第一间隔物。 在间隔物形成之后,该过程继续蚀刻直接在第一间隔物下面和之间的区域,暴露第一间隔物的下侧,形成覆盖第一间隔物的所有暴露部分的第二间隔区,其中除去氧化垫层, 第一半导体晶片上的栅极结构。

    Method to improve wet etch budget in FEOL integration
    5.
    发明授权
    Method to improve wet etch budget in FEOL integration 失效
    在FEOL集成中改善湿法蚀刻预算的方法

    公开(公告)号:US08679941B2

    公开(公告)日:2014-03-25

    申请号:US13422138

    申请日:2012-03-16

    IPC分类号: H01L21/76

    CPC分类号: H01L21/76229

    摘要: A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.

    摘要翻译: 提供一种形成半导体器件的方法,其中在一个实施例中,STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。 至少形成凹入的STI填充材料的上表面,形成薄(具有在约10埃-120埃范围内的厚度)耐湿蚀刻层。 薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。 薄的耐湿蚀刻层可以是耐火电介质材料,或诸如HfO x,Al y O x,ZrO x,HfZrO x和HfSiO x的电介质。 本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

    METHOD TO IMPROVE WET ETCH BUDGET IN FEOL INTEGRATION
    8.
    发明申请
    METHOD TO IMPROVE WET ETCH BUDGET IN FEOL INTEGRATION 失效
    提高生产费用总额的方法

    公开(公告)号:US20120178236A1

    公开(公告)日:2012-07-12

    申请号:US13422138

    申请日:2012-03-16

    IPC分类号: H01L21/762

    CPC分类号: H01L21/76229

    摘要: A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.

    摘要翻译: 提供一种形成半导体器件的方法,其中在一个实施例中,STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。 至少形成凹入的STI填充材料的上表面,形成薄(具有在约10埃-120埃范围内的厚度)耐湿蚀刻层。 薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。 薄的耐湿蚀刻层可以是耐火电介质材料,或诸如HfO x,Al y O x,ZrO x,HfZrO x和HfSiO x的电介质。 本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

    Method to improve wet etch budget in FEOL integration
    9.
    发明授权
    Method to improve wet etch budget in FEOL integration 有权
    在FEOL集成中改善湿法蚀刻预算的方法

    公开(公告)号:US08232179B2

    公开(公告)日:2012-07-31

    申请号:US12571483

    申请日:2009-10-01

    IPC分类号: H01L21/76

    CPC分类号: H01L21/76229

    摘要: A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.

    摘要翻译: 提供一种形成半导体器件的方法,其中在一个实施例中,STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。 至少形成凹入的STI填充材料的上表面,形成薄(具有在约10埃-120埃范围内的厚度)耐湿蚀刻层。 薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。 薄的耐湿蚀刻层可以是耐火电介质材料,或诸如HfO x,Al y O x,ZrO x,HfZrO x和HfSiO x的电介质。 本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。