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    LOW SERIES RESISTANCE TRANSISTOR STRUCTURE ON SILICON ON INSULATOR LAYER
    1.
    发明申请
    LOW SERIES RESISTANCE TRANSISTOR STRUCTURE ON SILICON ON INSULATOR LAYER 有权
    绝缘体层上硅的低串联电阻晶体管结构

    公开(公告)号：US20130175625A1

    公开(公告)日：2013-07-11

    申请号：US13622712

    申请日：2012-09-19

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Amlan Majumdar ,  Sanjay Mehta

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Amlan Majumdar ,  Sanjay Mehta

    IPC分类号： H01L29/78

    CPC分类号： H01L21/2255 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636

    摘要： A transistor structure includes a channel located in an extremely thin silicon on insulator (ETSOI) layer and disposed between a raised source and a raised drain, a gate structure having a gate conductor disposed over the channel and between the source and the drain, and a gate spacer layer disposed over the gate conductor. The raised source and the raised drain each have a facet that is upwardly sloping away from the gate structure. A lower portion of the source and a lower portion of the drain are separated from the channel by an extension region containing a dopant species diffused from a dopant-containing glass.

    摘要翻译： 晶体管结构包括位于极薄的绝缘体上硅（ETSOI）层上的通道，并且设置在升高的源极和升高的漏极之间的栅极结构，栅极结构具有布置在沟道上方以及源极与漏极之间的栅极结构，以及 栅极间隔层设置在栅极导体上。 升高的源极和升高的漏极各自具有远离栅极结构向上倾斜的小面。 源极的下部和漏极的下部通过包含从含掺杂剂的玻璃扩散的掺杂​​物种的延伸区与沟道分离。

    Robust isolation for thin-box ETSOI MOSFETS
    2.
    发明授权
    Robust isolation for thin-box ETSOI MOSFETS 有权
    薄型ETSOI MOSFET的强大隔离性

    公开(公告)号：US08927387B2

    公开(公告)日：2015-01-06

    申请号：US13442168

    申请日：2012-04-09

    申请人： Kangguo Cheng ,  Bruce B Doris ,  Balasubramanian S Haran ,  Sanjay Mehta ,  Stefan Schmitz

    发明人： Kangguo Cheng ,  Bruce B Doris ,  Balasubramanian S Haran ,  Sanjay Mehta ,  Stefan Schmitz

    IPC分类号： H01L27/088 ,  H01L21/336 ,  H01L21/762

    CPC分类号： H01L21/84 ,  H01L21/76283 ,  H01L27/1203

    摘要： A thin BOX ETSOI device with robust isolation and method of manufacturing. The method includes providing a wafer with at least a pad layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less. The process continues with etching a shallow trench into the wafer, extending partially into the second semiconductor layer and forming first spacers on the sidewalls of said shallow trench. After spacer formation, the process continues by etching an area directly below and between the first spacers, exposing the underside of the first spacers, forming second spacers covering all exposed portions of the first spacers, wherein the pad oxide layer is removed, and forming a gate structure over the first semiconductor wafer.

    摘要翻译： 薄型BOX ETSOI器件，具有强大的隔离性和制造方法。 该方法包括提供晶片至少一覆盖在覆盖第二半导体层的氧化物层上的第一半导体层的焊盘层，其中第一半导体层具有10nm或更小的厚度。 该过程继续蚀刻到晶片中的浅沟槽，部分地延伸到第二半导体层中并且在所述浅沟槽的侧壁上形成第一间隔物。 在间隔物形成之后，该过程继续蚀刻直接在第一间隔物下面和之间的区域，暴露第一间隔物的下侧，形成覆盖第一间隔物的所有暴露部分的第二间隔区，其中除去氧化垫层， 第一半导体晶片上的栅极结构。

    ROBUST ISOLATION FOR THIN-BOX ETSOI MOSFETS
    3.
    发明申请
    ROBUST ISOLATION FOR THIN-BOX ETSOI MOSFETS 有权
    用于薄盒ETSOI MOSFET的稳定隔离

    公开(公告)号：US20130264641A1

    公开(公告)日：2013-10-10

    申请号：US13442168

    申请日：2012-04-09

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Sanjay Mehta ,  Stefan Schmitz

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Sanjay Mehta ,  Stefan Schmitz

    IPC分类号： H01L27/088 ,  H01L21/762 ,  H01L21/336

    CPC分类号： H01L21/84 ,  H01L21/76283 ,  H01L27/1203

    摘要： A thin BOX ETSOI device with robust isolation and method of manufacturing. The method includes providing a wafer with at least a pad layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less. The process continues with etching a shallow trench into the wafer, extending partially into the second semiconductor layer and forming first spacers on the sidewalls of said shallow trench. After spacer formation, the process continues by etching an area directly below and between the first spacers, exposing the underside of the first spacers, forming second spacers covering all exposed portions of the first spacers, wherein the pad oxide layer is removed, and forming a gate structure over the first semiconductor wafer.

    摘要翻译： 薄型BOX ETSOI器件，具有强大的隔离性和制造方法。 该方法包括提供晶片至少一覆盖在覆盖第二半导体层的氧化物层上的第一半导体层的焊盘层，其中第一半导体层具有10nm或更小的厚度。 该过程继续蚀刻到晶片中的浅沟槽，部分地延伸到第二半导体层中并且在所述浅沟槽的侧壁上形成第一间隔物。 在间隔物形成之后，该过程继续蚀刻直接在第一间隔物下面和之间的区域，暴露第一间隔物的下侧，形成覆盖第一间隔物的所有暴露部分的第二间隔区，其中除去氧化垫层， 第一半导体晶片上的栅极结构。

    Semiconductor substrate with transistors having different threshold voltages
    4.
    发明授权
    Semiconductor substrate with transistors having different threshold voltages 失效
    具有不同阈值电压的晶体管的半导体衬底

    公开(公告)号：US08642415B2

    公开(公告)日：2014-02-04

    申请号：US13487511

    申请日：2012-06-04

    申请人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Pranita Kulkarni ,  Alexander Reznicek

    发明人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Pranita Kulkarni ,  Alexander Reznicek

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/1203 ,  H01L21/84

    摘要： A method of creating a semiconductor integrated circuit is disclosed. The method includes forming a first field effect transistor (FET) device and a second FET device on a semiconductor substrate. The method includes epitaxially growing raised source/drain (RSD) structures for the first FET device at a first height. The method includes epitaxially growing raised source/drain (RSD) structures for the second FET device at a second height. The second height is greater than the first height such that a threshold voltage of the second FET device is greater than a threshold voltage of the first FET device.

    摘要翻译： 公开了一种制造半导体集成电路的方法。 该方法包括在半导体衬底上形成第一场效应晶体管（FET）器件和第二FET器件。 该方法包括在第一高度上外延生长用于第一FET器件的升高的源极/漏极（RSD）结构。 该方法包括在第二高度上外延生长用于第二FET器件的升高的源极/漏极（RSD）结构。 第二高度大于第一高度，使得第二FET器件的阈值电压大于第一FET器件的阈值电压。

    UNDERCUT INSULATING REGIONS FOR SILICON-ON-INSULATOR DEVICE
    6.
    发明申请
    UNDERCUT INSULATING REGIONS FOR SILICON-ON-INSULATOR DEVICE 有权
    用于绝缘体绝缘体器件的绝缘绝缘区域

    公开(公告)号：US20140001555A1

    公开(公告)日：2014-01-02

    申请号：US13537141

    申请日：2012-06-29

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/0649 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/78 ,  H01L29/7838

    摘要： A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer. The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region. A field effect transistor (FET) device is formed on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET.

    摘要翻译： 制造绝缘体上硅（SOI）半导体器件的方法包括将底切隔离沟槽蚀刻成SOI衬底，所述SOI衬底包括底部衬底，形成在底部衬底上的掩埋氧化物（BOX）层，以及顶部 SOI层，其形成在BOX层上，其中底切隔离沟槽延伸穿过顶部SOI层和BOX层并进入底部衬底，使得底切绝缘沟槽的一部分位于BOX层下方的底部衬底中。 底切隔离槽填充有包括绝缘材料的底切填充物以形成底切隔离区域。 在与底切隔离区相邻的顶部SOI层上形成场效应晶体管（FET）器件，其中底切隔离区延伸在FET的源极/漏极区的下方。