公开(公告)号：US20090017584A1

公开(公告)日：2009-01-15

申请号：US11776710

申请日：2007-07-12

申请人： Kangguo Cheng ,  Xi Li ,  Richard S. Wise

发明人： Kangguo Cheng ,  Xi Li ,  Richard S. Wise

IPC分类号： H01L29/786

CPC分类号： H01L29/66795 ,  H01L29/785

摘要： A process for finFET spacer formation generally includes depositing, in order, a conformnal liner material, a conformal spacer material, and a conformal capping material onto the finFET structure; tilt implanting dopant ions into portions of the capping layer about the gate structure; selectively removing undoped capping material about the source and drain regions; selectively removing exposed portions of the spacer material; selectively removing exposed portions of the capping material; anisotropically removing a portion of the spacer material so as to expose a top surface of the gate material and isolate the spacer material to sidewalls of the gate structure; and removing the oxide liner from the fin to form the spacer on the finFET structure.

摘要翻译： 用于finFET间隔物形成的方法通常包括依次将共形衬垫材料，共形隔离材料和保形封盖材料沉积到finFET结构上; 倾斜地将掺杂剂离子注入围绕栅极结构的覆盖层的部分; 围绕源极和漏极区域选择性地去除未掺杂的封盖材料; 选择性地去除间隔物材料的暴露部分; 选择性地去除封盖材料的暴露部分; 各向异性地去除间隔物材料的一部分，以露出栅极材料的顶表面并将间隔物材料隔离到栅极结构的侧壁; 以及从翅片上去除氧化物衬垫以在finFET结构上形成间隔物。

公开(公告)号：US07476578B1

公开(公告)日：2009-01-13

申请号：US11776710

申请日：2007-07-12

申请人： Kangguo Cheng ,  Xi Li ,  Richard S. Wise

发明人： Kangguo Cheng ,  Xi Li ,  Richard S. Wise

IPC分类号： H01L21/00

CPC分类号： H01L29/66795 ,  H01L29/785

摘要： A process for finFET spacer formation generally includes depositing, in order, a conformal liner material, a conformal spacer material, and a conformal capping material onto the finFET structure; tilt implanting dopant ions into portions of the capping layer about the gate structure; selectively removing undoped capping material about the source and drain regions; selectively removing exposed portions of the spacer material; selectively removing exposed portions of the capping material; anisotropically removing a portion of the spacer material so as to expose a top surface of the gate material and isolate the spacer material to sidewalls of the gate structure; and removing the oxide liner from the fin to form the spacer on the finFET structure.

摘要翻译： 用于finFET间隔物形成的方法通常包括依次将共形衬垫材料，共形隔离材料和保形封盖材料沉积到finFET结构上; 倾斜地将掺杂剂离子注入围绕栅极结构的覆盖层的部分; 围绕源极和漏极区域选择性地去除未掺杂的封盖材料; 选择性地去除间隔物材料的暴露部分; 选择性地去除封盖材料的暴露部分; 各向异性地去除间隔物材料的一部分，以露出栅极材料的顶表面并将间隔物材料隔离到栅极结构的侧壁; 以及从翅片上去除氧化物衬垫以在finFET结构上形成间隔物。

公开(公告)号：US08492280B1

公开(公告)日：2013-07-23

申请号：US13465050

申请日：2012-05-07

申请人： Habib Hichri ,  Xi Li ,  Richard S. Wise

发明人： Habib Hichri ,  Xi Li ,  Richard S. Wise

IPC分类号： H01L21/311

CPC分类号： H01L21/3065 ,  H01L21/76229 ,  H01L21/84 ,  H01L27/1087 ,  H01L29/66181

摘要： Embodiments of the invention may include first providing a stack of layers including a semiconductor substrate, a buried oxide layer on the semiconductor substrate, a semiconductor-on-insulator layer on the buried-oxide layer, a nitride layer on the semiconductor-on-insulator layer, and a silicon oxide layer on the nitride layer. A first opening and second opening with a smaller cross-sectional area than the first opening are then formed in the silicon oxide layer, the nitride layer, the semiconductor-on-insulator layer, and the buried-oxide layer. The first opening and the second opening are then etched with a first etching gas. The first opening and the second opening are then etched with a second etching gas, which includes the first etching gas and a halogenated silicon compound, for example, silicon tetrafluoride or silicon tetrachloride. In one embodiment, the first etching gas includes hydrogen bromide, nitrogen trifluoride, and oxygen.

摘要翻译： 本发明的实施例可以包括首先提供包括半导体衬底，半导体衬底上的掩埋氧化物层，掩埋氧化物层上的绝缘体上半导体层，绝缘体上半导体上的氮化物层 层和氮化物层上的氧化硅层。 然后在氧化硅层，氮化物层，绝缘体上半导体层和掩埋氧化物层上形成具有比第一开口更小的横截面面积的第一开口和第二开口。 然后用第一蚀刻气体蚀刻第一开口和第二开口。 然后用第二蚀刻气体蚀刻第一开口和第二开口，第二蚀刻气体包括第一蚀刻气体和卤化硅化合物，例如四氟化硅或四氯化硅。 在一个实施方案中，第一蚀刻气体包括溴化氢，三氟化氮和氧。

公开(公告)号：US07498271B1

公开(公告)日：2009-03-03

申请号：US12145035

申请日：2008-06-24

申请人： Ricardo A. Donaton ,  Rashmi Jha ,  Siddarth A. Krishnan ,  Xi Li ,  Renee T. Mo ,  Naim Moumen ,  Wesley C. Natzle ,  Ravikumar Ramachandran ,  Richard S. Wise

发明人： Ricardo A. Donaton ,  Rashmi Jha ,  Siddarth A. Krishnan ,  Xi Li ,  Renee T. Mo ,  Naim Moumen ,  Wesley C. Natzle ,  Ravikumar Ramachandran ,  Richard S. Wise

IPC分类号： H01L21/31

CPC分类号： H01L21/31138 ,  H01L21/28202 ,  H01L21/31155 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： The present invention, in one embodiment, provides a method of forming a gate structure including providing a substrate including a semiconducting device region, a high-k dielectric material present atop the semiconducting device region, and a metal gate conductor atop the high-k dielectric material, applying a photoresist layer atop the metal gate conductor; patterning the photoresist layer to provide an etch mask overlying a portion of the metal gate conductor corresponding to a gate stack; etching the metal gate conductor and the high-k dielectric material selective to the etch mask; and removing the etch mask with a substantially oxygen free nitrogen based plasma.

摘要翻译： 本发明在一个实施例中提供了一种形成栅极结构的方法，该栅极结构包括提供包括半导体器件区域的衬底，在半导体器件区域顶部存在的高k电介质材料以及高k电介质顶部的金属栅极导体 材料，在金属栅极导体顶上施加光致抗蚀剂层; 图案化光致抗蚀剂层以提供覆盖对应于栅极堆叠的金属栅极导体的一部分的蚀刻掩模; 蚀刻对蚀刻掩模有选择性的金属栅极导体和高k电介质材料; 并用基本上不含氧的氮气等离子体去除蚀刻掩模。

公开(公告)号：US07833872B2

公开(公告)日：2010-11-16

申请号：US11931112

申请日：2007-10-31

申请人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  Xi Li

发明人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  Xi Li

IPC分类号： H01L21/20 ,  H01L21/311

CPC分类号： H01L21/32137 ,  H01L21/32115 ,  H01L29/66181

摘要： Columnar elements which extend to varying heights above a major surface of a substrate, e.g., polysilicon studs within trenches in the substrate, are recessed to a uniform depth below the major surface. The columnar elements are etched selectively with respect to a material exposed at the surface in an at least partly lateral direction so that the columnar elements are recessed to a uniform depth below the major surface at walls of the trenches.

摘要翻译： 在衬底的主表面上方延伸到不同高度的柱状元件（例如衬底中的沟槽内的多晶硅柱）凹陷到主表面下方的均匀深度。 相对于在表面上以至少部分横向方向暴露的材料，柱状元件被选择性地蚀刻，使得柱状元件在沟槽的壁处凹陷到主表面下方的均匀深度。

公开(公告)号：US07749835B2

公开(公告)日：2010-07-06

申请号：US12048263

申请日：2008-03-14

申请人： Xi Li ,  Kangguo Cheng ,  Johnathan Faltermeier

发明人： Xi Li ,  Kangguo Cheng ,  Johnathan Faltermeier

IPC分类号： H01L21/84 ,  H01L21/8242

CPC分类号： H01L29/945 ,  H01L21/32137 ,  H01L21/76232 ,  H01L21/84 ,  H01L27/1087 ,  H01L29/66181

摘要： A semiconductor structure is described. The structure includes a trench opening formed in a semiconductor substrate having a semiconductor-on-insulator (SOI) layer and a buried insulating (BOX) layer; and a filling material formed in the trench opening, the filling material forming a “V” shape within the trench memory cell, wherein the “V” shape includes a top portion substantially adjacent to a top surface of the BOX layer. A method of fabricating the semiconductor structure is also described. The method includes forming a trench opening in a semiconductor substrate having an SOI layer and a BOX layer; laterally etching the BOX layer such that a portion of the trench opening associated with the BOX layer is substantially greater than a portion of the trench opening associated with the SOI layer; filling the trench opening with a filling material; and recessing the filling material.

摘要翻译： 描述半导体结构。 该结构包括形成在具有绝缘体上半导体（SOI）层和掩埋绝缘（BOX）层的半导体衬底中的沟槽开口; 以及形成在所述沟槽开口中的填充材料，所述填充材料在所述沟槽存储单元内形成“V”形，其中所述“V”形包括基本上邻近所述BOX层的顶表面的顶部。 还描述了制造半导体结构的方法。 该方法包括在具有SOI层和BOX层的半导体衬底中形成沟槽开口; 横向蚀刻BOX层，使得与BOX层相关联的沟槽开口的一部分基本上大于与SOI层相关联的沟槽开口的一部分; 用填充材料填充沟槽开口; 并使填充材料凹陷。

公开(公告)号：US07560387B2

公开(公告)日：2009-07-14

申请号：US11275707

申请日：2006-01-25

申请人： Scott D. Allen ,  Kangguo Cheng ,  Xi Li ,  Kevin R. Winstel

发明人： Scott D. Allen ,  Kangguo Cheng ,  Xi Li ,  Kevin R. Winstel

IPC分类号： H01L21/311

CPC分类号： H01L21/3081 ,  H01L21/31116

摘要： Methods for opening a hard mask and a silicon-on-insulator substrate in a single process chamber are disclosed. In one embodiment, the method includes patterning a photoresist over a stack including an anti-reflective coating (ARC) layer, a silicon dioxide (SiO2) based hard mask layer, a silicon nitride pad layer, a silicon dioxide (SiO2) pad layer and the SOI substrate, wherein the SOI substrate includes a silicon-on-insulator layer and a buried silicon dioxide (SiO2) layer; and in a single process chamber: opening the ARC layer; etching the silicon dioxide (SiO2) based hard mask layer; etching the silicon nitride pad layer; etching the silicon dioxide (SiO2) pad layer; and etching the SOI substrate. Etching all layers in a single chamber reduces the turn-around-time, lowers the process cost, facilitates process control and/or improve a trench profile.

摘要翻译： 公开了在单个处理室中打开硬掩模和绝缘体上硅衬底的方法。 在一个实施例中，该方法包括在包括抗反射涂层（ARC）层，基于二氧化硅（SiO 2）的硬掩模层，氮化硅衬垫层，二氧化硅（SiO 2）衬垫层和叠层 SOI衬底，其中所述SOI衬底包括绝缘体上硅层和掩埋二氧化硅（SiO 2）层; 并在单个处理室中：打开ARC层; 蚀刻基于二氧化硅（SiO 2）的硬掩模层; 蚀刻氮化硅焊盘层; 蚀刻二氧化硅（SiO 2）垫层; 并蚀刻SOI衬底。 在单个室中蚀刻所有层减少了周转时间，降低了工艺成本，便于工艺控制和/或改善沟槽轮廓。

公开(公告)号：US20090108306A1

公开(公告)日：2009-04-30

申请号：US11931112

申请日：2007-10-31

申请人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  Xi Li

发明人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  Xi Li

IPC分类号： H01L29/94 ,  H01L21/311

CPC分类号： H01L21/32137 ,  H01L21/32115 ,  H01L29/66181

摘要： Columnar elements which extend to varying heights above a major surface of a substrate, e.g., polysilicon studs within trenches in the substrate, are recessed to a uniform depth below the major surface. The columnar elements are etched selectively with respect to a material exposed at the surface in an at least partly lateral direction so that the columnar elements are recessed to a uniform depth below the major surface at walls of the trenches.

摘要翻译： 在衬底的主表面上方延伸到不同高度的柱状元件（例如衬底中的沟槽内的多晶硅柱）凹陷到主表面下方的均匀深度。 相对于在表面上以至少部分横向方向暴露的材料选择性地蚀刻柱状元件，使得柱状元件在沟槽的壁处凹陷到主表面下方的均匀深度。

公开(公告)号：US07494891B2

公开(公告)日：2009-02-24

申请号：US11533928

申请日：2006-09-21

申请人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  Xi Li

发明人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  Xi Li

IPC分类号： H01L21/20

CPC分类号： H01L29/945 ,  H01L29/66181

摘要： A method forms a node dielectric in a bottle shaped trench and then deposits an initial conductor within the lower portion of the bottle shaped trench, such that a void is formed within the initial conductor. Next, the method forms an insulating collar in the upper portion of the bottle shaped trench above the initial conductor. Then, the method simultaneously etches a center portion of the insulating collar and the initial conductor until the void is exposed. This etching process forms a center opening within the insulating collar and the initial conductor. Additional conductor is deposited in the center opening such that the additional conductor is formed at least to the level of the surface of the substrate.

摘要翻译： 一种方法在瓶形沟槽中形成节点电介质，然后将初始导体沉积在瓶形沟槽的下部，使得在初始导体内形成空隙。 接下来，该方法在初始导体上方的瓶形沟槽的上部形成绝缘套环。 然后，该方法同时蚀刻绝缘套环的中心部分和初始导体，直到暴露出空隙。 该蚀刻工艺在绝缘环和初始导体内形成中心开口。 附加导体沉积在中心开口中，使得附加导体至少形成至基底表面的水平。

公开(公告)号：US20080248625A1

公开(公告)日：2008-10-09

申请号：US12120535

申请日：2008-05-14

申请人： Kangguo Cheng ,  David M. Dobuzinsky ,  Xi Li

发明人： Kangguo Cheng ,  David M. Dobuzinsky ,  Xi Li

IPC分类号： H01L21/441

CPC分类号： H01L29/945 ,  H01L28/84 ,  H01L29/66181

摘要： Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor. The rough sidewall enhances trench capacitance without increasing processing complexity or cost.