公开(公告)号：US20120199470A1

公开(公告)日：2012-08-09

申请号：US13364740

申请日：2012-02-02

申请人： Kaoru MORI ,  Eiji KARIYADA ,  Katsumi SUEMITSU ,  Norikazu OHSHIMA

发明人： Kaoru MORI ,  Eiji KARIYADA ,  Katsumi SUEMITSU ,  Norikazu OHSHIMA

IPC分类号： C23C14/34 ,  C23C14/06

CPC分类号： H01L43/12 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3236 ,  H01F10/3254 ,  H01F10/3286 ,  H01F41/307 ,  H01L43/08

摘要： A method for manufacturing an MTJ film includes forming a first ferromagnetic layer; forming a tunnel barrier layer over the first ferromagnetic layer; and forming a second ferromagnetic layer over the tunnel barrier layer. The first ferromagnetic layer is a Co/Ni stacked film having perpendicular magnetic anisotropy. The step for forming a tunnel barrier layer includes repeating unit film formation treatment n times (n is an integer of 2 or more). The unit film formation treatment includes the steps of: depositing an Mg film by a sputtering method; and oxidizing the deposited Mg film. A film thickness of the deposited Mg film in the first unit film formation treatment is 0.3 nm or more and 0.5 nm or less. A film thickness of the deposited Mg film in the second unit film formation treatment or later is 0.1 nm or more and 0.45 nm or less.

摘要翻译： 制造MTJ薄膜的方法包括：形成第一铁磁层; 在所述第一铁磁层上形成隧道势垒层; 以及在所述隧道势垒层上形成第二铁磁层。 第一铁磁层是具有垂直磁各向异性的Co / Ni叠层膜。 形成隧道势垒层的步骤包括重复单元成膜处理n次（n为2以上的整数）。 单元成膜处理包括以下步骤：通过溅射法沉积Mg膜; 并氧化沉积的Mg膜。 第一单位成膜处理中的沉积的Mg膜的膜厚为0.3nm以上且0.5nm以下。 在第二单元成膜处理中或之后的沉积的Mg膜的膜厚度为0.1nm以上且0.45nm以下。

公开(公告)号：US20120057420A1

公开(公告)日：2012-03-08

申请号：US13279111

申请日：2011-10-21

申请人： Kaoru MORI

发明人： Kaoru MORI

IPC分类号： G11C29/00 ,  G11C8/00

CPC分类号： G11C29/16 ,  G11C2029/1804

摘要： A semiconductor memory in which arbitrary operation mode information is set in a plurality of CRs at test time. When a CR control circuit detects write commands to write to an address or read commands to read from the address in a predetermined order, the CR control circuit updates the operation mode information for each of the plurality of CRs on a time division basis. A command generation section generates the write commands, the read commands, or a test start command in response to a control signal from the outside. A data pad compression circuit changes the operation mode information to be written to the plurality of CRs by using test data inputted to part of data pads, after inverting the test data or in its original condition according to a code, as data for a rest of the data pads.

摘要翻译： 一种在测试时间内在多个CR中设定任意操作模式信息的半导体存储器。 当CR控制电路检测到写入命令以写入地址或读取以预定顺序从地址读取的命令时，CR控制电路基于时分更新多个CR中的每一个的操作模式信息。 命令生成部分响应于来自外部的控制信号生成写命令，读命令或测试开始命令。 数据块压缩电路通过使用输入到数据块的一部分的测试数据，在将测试数据或其原始状态根据代码反转之后，将待写入的操作模式信息改变为用于其余部分的数据 数据垫。

公开(公告)号：US20110255347A1

公开(公告)日：2011-10-20

申请号：US13020636

申请日：2011-02-03

申请人： Kaoru MORI ,  Toshiya Uchida

发明人： Kaoru MORI ,  Toshiya Uchida

IPC分类号： G11C16/06

CPC分类号： G11C16/26 ,  G11C7/18 ,  G11C7/227 ,  G11C16/24 ,  G11C16/32

摘要： A semiconductor memory includes a sense amplifier which operates in response to activation of a sense amplifier enable signal and determines logic held in a nonvolatile memory cell according to a voltage of a bit line, the voltage varying with a cell current flowing through a real cell transistor, a replica cell transistor coupled in series between a first node and a ground line, and a timing generation unit. The timing generation unit activates the sense amplifier enable signal when the first node coupled to the ground line via the replica cell transistor changes from a high level to a low level. The replica cell transistor includes a control gate receiving a constant voltage and a floating gate coupled to the control gate. Thus, the activation timing of the sense amplifier can be optimally set in accordance with the electric characteristic of the memory cell.

摘要翻译： 半导体存储器包括读出放大器，其响应于读出放大器使能信号的激活而操作，并且根据位线的电压确定保持在非易失性存储器单元中的逻辑，该电压随着流过真实单元晶体管的单元电流而变化 耦合在第一节点和地线之间的复制单元晶体管，以及定时产生单元。 当通过复制单元晶体管耦合到接地线的第一节点从高电平变为低电平时，定时生成单元激活读出放大器使能信号。 复制单元晶体管包括接收恒定电压的控制栅极和耦合到控制栅极的浮置栅极。 因此，可以根据存储单元的电特性来最佳地设置感测放大器的激活定时。

公开(公告)号：US20110167307A1

公开(公告)日：2011-07-07

申请号：US13050633

申请日：2011-03-17

申请人： Kaoru MORI

发明人： Kaoru MORI

IPC分类号： G11C29/00 ,  G06F11/267

CPC分类号： G11C29/16 ,  G11C2029/1804

摘要： A semiconductor memory in which arbitrary operation mode information is set in a plurality of CRs at test time and by which a test cost is reduced and a method for testing such a semiconductor memory. The plurality of CRs hold operation mode information. When a CR control circuit detects write commands to write to an address for register access or read commands to read from the address for register access in a predetermined order, the CR control circuit updates the operation mode information for each of the plurality of CRs on a time division basis. A command generation section generates the write commands, the read commands, or a test start command by which write operation or read operation does not occur, in response to a control signal from the outside. In addition, the command generation section regenerates the test start command each time the plurality of CRs are updated. A data pad compression circuit changes the operation mode information to be written to the plurality of CRs by using test data inputted to part of data pads, after inverting the test data or in its original condition according to a code, as data for a rest of the data pads, the code represented by part of an address inputted at the time of the test start command being sent.

摘要翻译： 一种半导体存储器，其中在测试时间内在多个CR中设置任意操作模式信息，并且测试成本降低，并且测试这种半导体存储器的方法。 多个CR保持操作模式信息。 当CR控制电路检测写入命令以写入寄存器访问的地址或读取命令以按预定顺序从地址读取寄存器访问时，CR控制电路更新在多个CR中的每一个的操作模式信息 时分基础。 响应于来自外部的控制信号，命令生成部分生成写入命令，读取命令或者不发生写入操作或读取操作的测试开始命令。 另外，每当更新多个CR时，命令生成部重新生成测试开始命令。 数据块压缩电路通过使用输入到数据块的一部分的测试数据，在将测试数据或其原始状态根据代码反转之后，将待写入的操作模式信息改变为用于其余部分的数据 数据焊盘，由发送测试开始命令时输入的地址的一部分表示的代码。

公开(公告)号：US20100110818A1

公开(公告)日：2010-05-06

申请号：US12684652

申请日：2010-01-08

申请人： Kaoru MORI ,  Shinya Fujioka ,  Yoshitaka Takahashi ,  Jun Ohno ,  Akihiro Funyu ,  Shinichiro Suzuki

发明人： Kaoru MORI ,  Shinya Fujioka ,  Yoshitaka Takahashi ,  Jun Ohno ,  Akihiro Funyu ,  Shinichiro Suzuki

IPC分类号： G11C7/00 ,  H03K17/00 ,  H03K17/56 ,  G11C8/00

CPC分类号： G11C7/04 ,  G11C11/406 ,  G11C11/40626 ,  G11C11/4072 ,  G11C11/4074

摘要： There is provided a semiconductor device including: a temperature sensor detecting temperature; an inner circuit operating when supplied with a power supply voltage from a power supply line; a switch connected between the power supply line and the inner circuit; and a control circuit performing control in which, in a case where the temperature detected by the temperature sensor is higher than a threshold value, the switch is turned on when the inner circuit is in operation and the switch is turned off when the inner circuit is in non-operation, and in a case where the temperature detected by the temperature sensor is lower than the threshold value, the switch is turned on when the inner circuit is in operation and in non-operation.

摘要翻译： 提供了一种半导体器件，包括：温度传感器检测温度; 当从电源线供给电源电压时工作的内部电路; 连接在电源线和内部电路之间的开关; 以及控制电路，其进行控制，其中，在由所述温度传感器检测到的温度高于阈值的情况下，当所述内部电路工作时所述开关接通，并且当所述内部电路为 在不工作的情况下，并且在由温度传感器检测到的温度低于阈值的情况下，当内部电路运行并且不工作时，开关导通。

公开(公告)号：US20090040851A1

公开(公告)日：2009-02-12

申请号：US12130578

申请日：2008-05-30

申请人： Kaoru MORI ,  Kota Hara ,  Jun Ohno

发明人： Kaoru MORI ,  Kota Hara ,  Jun Ohno

IPC分类号： G11C29/00 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C29/02 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4087 ,  G11C29/024 ,  G11C29/025 ,  G11C29/12015 ,  G11C2029/1202 ,  G11C2211/4061

摘要： Each sub word line is coupled to a gate of a transfer transistor of a memory cell. A first switch of a sub word decoder couples the sub word line to a high level voltage line when a main word line is in an activation level. A second switch couples the sub word line to a low level voltage line when the main word line is in an inactivation level. A third switch couples the sub word line to the low level voltage line when a word reset signal line is in an activation level. A reset control circuit disables the inactivation of the main word line or the activation of the word reset signal line during a test mode. One of the second and third switches is forcibly turned off, and thereby, an operation failure of a sub word decoder can be detected easily.

摘要翻译： 每个子字线耦合到存储器单元的转移晶体管的栅极。 当主字线处于激活电平时，子字解码器的第一开关将子字线耦合到高电平电压线。 当主字线处于钝化级别时，第二开关将子字线耦合到低电平电压线。 当字复位信号线处于激活电平时，第三开关将子字线耦合到低电平电压线。 复位控制电路在测试模式期间禁用主字线的失活或字复位信号线的激活。 第二和第三开关中的一个被强制关闭，从而可以容易地检测到子字解码器的操作故障。

公开(公告)号：US20090040849A1

公开(公告)日：2009-02-12

申请号：US12127161

申请日：2008-05-27

申请人： Kaoru MORI ,  Jun OHNO ,  Hiroyuki KOBAYASHI

发明人： Kaoru MORI ,  Jun OHNO ,  Hiroyuki KOBAYASHI

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C29/26 ,  G11C7/1045 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C2029/5006 ,  G11C2029/5602

摘要： Each program circuit outputs an operating specification signal indicating a first or second operating specification according to a program state. Each specification changing circuit is set by a corresponding block selection signal and outputs an operating specification signal indicating a second operating specification. Each timing control circuit changes an output timing of a precharge control signal for a bit line according to the operating specification signal. By the operating specification signal from the specification changing circuit, a failure can be detected in each memory block before programming a program circuit. Thereafter, the failure can be relieved by the program circuit. The output timing of the precharge control signal can be set for each memory block by a block selection signal without wiring a dedicated signal line for setting each specification changing circuit. Accordingly, increase in chip size can be minimized.

摘要翻译： 每个程序电路根据程序状态输出指示第一或第二操作规范的操作规范信号。 每个规格改变电路由相应的块选择信号设置，并输出指示第二操作规范的操作指定信号。 每个定时控制电路根据操作指定信号改变位线的预充电控制信号的输出定时。 通过来自规范改变电路的操作规范信号，在对程序电路进行编程之前可以在每个存储器块中检测到故障。 此后，程序电路可以解除故障。 可以通过块选择信号为每个存储器块设置预充电控制信号的输出定时，而不布线用于设置每个规格改变电路的专用信号线。 因此，可以使芯片尺寸的增加最小化。