公开(公告)号：US4002928A

公开(公告)日：1977-01-11

申请号：US506840

申请日：1974-09-17

Applicant: Karl Goser ,  Michael Pomper

Inventor： Karl Goser ,  Michael Pomper

IPC: H03K19/018 ,  H03K5/02 ,  H03K17/687 ,  H03K23/50 ,  H03K17/60 ,  H03K19/08

CPC classification number: H03K23/505 ,  H03K5/023

Abstract: Two semiconductor chips having complementary MOS circuits are interconnected by means of an output stage provided on the first chip and an input stage provided on the second chip. The connection is a high-speed connection despite the relatively high internal impedance of the MOS transistors. The output stage incorporates MOS transistors for transforming the signal level to a relatively low level, and the input stage incorporates MOS transistors interconnected as a pulsed trigger or amplifier for restoring the low signal to a relatively high level for connection to other MOS circuits.

Abstract translation: 具有互补MOS电路的两个半导体芯片通过设置在第一芯片上的输出级和设置在第二芯片上的输入级互连。 连接是高速连接，尽管MOS晶体管的内部阻抗相对较高。 输出级包含用于将信号电平变换为相对较低电平的MOS晶体管，并且输入级包含作为脉冲触发或放大器互连的MOS晶体管，用于将低信号恢复到较高电平以连接到其它MOS电路。

公开(公告)号：US4307355A

公开(公告)日：1981-12-22

申请号：US69873

申请日：1979-08-27

Applicant: Karl Goser

Inventor： Karl Goser

IPC: H03H15/02 ,  G11C19/28 ,  G11C27/04 ,  H03H17/04 ,  G11C27/00 ,  H03H21/00

CPC classification number: G11C19/285 ,  G11C27/04

Abstract: The invention relates to a method for operating recursive filter circuits or analog storage circuits constructed according to the charge coupled device principle and relates to a circuit arrangement for implementing the method, in which method only each respective second stage of a CCD is occupied with a charge representing a sampling value of an analog signal and the respective stages lying between these stages concerned and left empty. Known circuits constructed according to the CCD principle conduct the signal from the output stage of a CCD chain to the input of the CCD loop via an amplifier to which the input signal is supplied at the same time. Thereby, the amplification must very precisely amount to one. An amplifier of the high stability required thereto which is arranged in common with the concerned CCD on a chip cannot be satisfactorily realized. By means of the invention, a method is specified in which the amplifier is replaced by means of modulation of a sampling value with a reference signal and by means of a charge amount corrected in accord with the result of the modulation.

Abstract translation: 本发明涉及一种用于操作根据电荷耦合器件原理构造的递归滤波器电路或模拟存储电路的方法，并且涉及一种用于实现该方法的电路装置，其中仅CCD的每个相应的第二级占用电荷 表示模拟信号的采样值和位于这些相关级之间的相应级并且为空。 根据CCD原理构造的已知电路通过同时提供输入信号的放大器将信号从CCD链的输出级传送到CCD环路的输入。 因此，放大必须非常精确地达到1。 与芯片上的相关CCD共同设置的高稳定性的放大器不能令人满意地实现。 通过本发明，规定了一种方法，其中通过利用参考信号调制采样值并借助于根据调制结果校正的电荷量来替换放大器。

公开(公告)号：US06321216B1

公开(公告)日：2001-11-20

申请号：US08982613

申请日：1997-12-02

Applicant: Ralf Otte ,  Gerd Rappenecker ,  Karl Goser

Inventor： Ralf Otte ,  Gerd Rappenecker ,  Karl Goser

IPC: G06F1518

CPC classification number: G06N3/04 ,  G05B19/0425 ,  Y10S706/906 ,  Y10S706/907

Abstract: A method for analyzing and displaying process states of a technical plant includes enabling simultaneous, coherent assessment and display of relevant process variables of the plant by evaluating relevant process variables with regard to one another through the use of a neural analysis on the basis of self-organizing maps, by making a topology-producing projection of data of the relevant process variables onto a neural map. The current process courses are plotted as trajectories on the map. Evaluation in the sense of a diagnosis can be carried out either visually or in an automated manner.

Abstract translation: 一种用于分析和显示技术工厂的过程状态的方法包括通过使用基于自身的神经分析来评估相关的相关过程变量来实现工厂的相关过程变量的同步，连贯的评估和显示。 通过将相关过程变量的数据的拓扑生成投影到神经图上来组织地图。 目前的过程课程作为轨迹绘制在地图上。 在诊断意义上的评估可以在视觉上或以自动方式进行。

公开(公告)号：US3999166A

公开(公告)日：1976-12-21

申请号：US495185

申请日：1974-08-06

Applicant: Karl Goser ,  Michael Pomper

Inventor： Karl Goser ,  Michael Pomper

IPC: G11C11/412 ,  G11C11/40 ,  G11C13/00

CPC classification number: G11C11/412 ,  Y10S257/903

Abstract: A static semiconductor storage element includes a flip-flop formed of a pair of complementary field effect transistors which are cross coupled without intersection to form a bistable circuit. One node of the flip-flop is connected to a terminal which is employed for both reading and writing functions. The flip-flop is set or reset by connection of an appropriate voltage to the node, and nondestructive read out is carried out by sensing the voltage level of the node.

Abstract translation: 静态半导体存储元件包括由一对互补的场效应晶体管形成的触发器，其互不交叉而形成双稳态电路。 触发器的一个节点连接到用于读取和写入功能的终端。 通过将适当的电压连接到节点来设置或复位触发器，并且通过感测节点的电压电平来执行非破坏性读出。

公开(公告)号：US3975718A

公开(公告)日：1976-08-17

申请号：US509309

申请日：1974-09-25

Applicant: Karl Goser

Inventor： Karl Goser

IPC: G11C11/41 ,  G11C11/405 ,  G11C11/412 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H03K3/356 ,  G11C11/40

CPC classification number: G11C11/412 ,  H01L27/0883 ,  H01L27/092 ,  H01L27/12 ,  H03K3/356104

Abstract: A storage arrangement employing first and second field effect transistors which are complementary to one another and connected in series, with the second transistor being of the depletion type, a load element, such as a resistor or transistor, being connected in series with such first mentioned transistors, with one side of such load element connected to the drain terminal of the first transistor and the other side of such load element connected to a line to which a supply voltage is connected, the drain-terminal of the second transistor being connected to a second line, which may form a word line, the gate terminal of the second transistor being connected to the drain terminal of the first transistor, and, preferably, a selector element such as a diode or transistor being operatively disposed between a third line and the junction of the load element and drain terminal of said first transistor, which third line may form a bit line, and a method of operating such arrangement.

Abstract translation: 一种采用第一和第二场效应晶体管的存储装置，第一和第二场效应晶体管彼此互补并且串联连接，第二晶体管是耗尽型，负载元件如电阻器或晶体管与这种第一提及的串联连接 晶体管，这种负载元件的一侧连接到第一晶体管的漏极端子，并且该负载元件的另一侧连接到与其连接的电源线，第二晶体管的漏极端子连接到 第二晶体管的栅极端子可以形成字线，第二晶体管的栅极端子连接到第一晶体管的漏极端子，并且优选地，诸如二极管或晶体管的选择器元件可操作地设置在第三线路与第三晶体管的漏极端子之间， 所述第一晶体管的负载元件和漏极端子的所述第三线可以形成位线，以及操作这种布置的方法。

公开(公告)号：US4283696A

公开(公告)日：1981-08-11

申请号：US69790

申请日：1979-08-27

Applicant: Karl Goser

Inventor： Karl Goser

IPC: G11C19/28 ,  G11C27/00 ,  G11C27/04 ,  H03H15/02 ,  H03H17/04

CPC classification number: H03H15/02 ,  G11C19/282 ,  G11C27/00 ,  G11C27/04

Abstract: The invention relates to a method for operating recursive filter circuits or analog storage circuits constructed according to the charge coupled device principle and to a circuit arrangement for implementing the method, in which method only each respective second stage a CCD is occupied with a charge representing a sampling value of an analog signal and the respective stages lying between these stages concerned are left empty. Known circuits constructed according to the CCD principle conduct the signal from the output stage of a CCD chain to the input of the CCD loop via an amplifier to which the input signal is supplied at the same time. Thereby, the amplification must very precisely amount to 1. An amplifier of the high stability required for that purpose which is arranged in common with the CCD concerned on a chip cannot be satisfactorily realized. A method is specified by means of the invention in which the amplifier is replaced by modulation of a sampling value with a reference signal and by means of a charge amount corrected in accord with the result of the modulation.

Abstract translation: 本发明涉及一种用于操作根据电荷耦合器件原理构造的递归滤波器电路或模拟存储电路的方法，以及用于实现该方法的电路装置，其中仅每个相应的第二级CCD被占用一个代表 模拟信号的采样值以及位于这些相关阶段之间的各个阶段是空的。 根据CCD原理构造的已知电路通过同时提供输入信号的放大器将信号从CCD链的输出级传送到CCD环路的输入。 因此，放大必须非常精确地等于1.与芯片相关的CCD共同设置的该目的所需的高稳定性的放大器不能令人满意地实现。 通过本发明规定了一种方法，其中放大器被具有参考信号的采样值的调制代替，并且借助于根据调制结果校正的电荷量来代替。

公开(公告)号：US4085339A

公开(公告)日：1978-04-18

申请号：US617965

申请日：1975-09-29

Applicant: Karl Goser ,  Ruediger Mueller

Inventor： Karl Goser ,  Ruediger Mueller

IPC: H01L27/00 ,  H01L27/02 ,  H01L27/12 ,  H03K19/08 ,  H03K19/22

CPC classification number: H01L27/0233 ,  H01L27/00

Abstract: A circuit arrangement CHL technique (current hogging logic) includes individual CHL arrangements each having an emitter, control collectors and an output collector and arranged within an epitaxial layer. The individual CHL arrangements are complementary with respect to one another, and arrangement of one conductivity type being directly integrated in the epitaxial layer and the arrangement which is complementary thereto being integrated in a basin in the epitaxial layer, the basin being doped opposite to the epitaxial layer.

Abstract translation: 电路布置CHL技术（电流调节逻辑）包括各自具有发射极，控制集电极和输出集电极并布置在外延层内的CHL布置。 单独的CHL布置彼此互补，并且直接集成在外延层中的一种导电类型的布置和与其互补的布置集成在外延层中的盆中，该盆与外延层相反地掺杂 层。

公开(公告)号：US4038676A

公开(公告)日：1977-07-26

申请号：US634038

申请日：1975-11-21

Applicant: Karl Goser

Inventor： Karl Goser

IPC: H01L21/331 ,  H01L21/8222 ,  H01L23/535 ,  H01L27/06 ,  H01L27/082 ,  H01L29/73 ,  H01L29/735 ,  H01L29/72 ,  H01L29/48 ,  H01L29/56 ,  H01L29/64

CPC classification number: H01L27/0688 ,  H01L21/8222 ,  H01L23/535 ,  H01L29/735 ,  H01L2924/0002

Abstract: A pair of bipolar transistors are formed in a semiconductor substrate with each transistor having at least one emitter, one base and at least one collector. At least the base is in the form of a doped zone in the substrate. The two base zones are electrically conductively connected to one another and the transistors are constructed or arranged in the substrate in such a manner that in each case free boundary faces of the two base zones lie opposite one another. The base connection is formed by an additionally doped zone in the interspace between the base zones, the doped zone having the same type of doping as the base zones.

公开(公告)号：US4250556A

公开(公告)日：1981-02-10

申请号：US10121

申请日：1979-02-06

Applicant: Karl Goser

Inventor： Karl Goser

IPC: G05B19/08 ,  G06G7/00 ,  G06G7/06 ,  G06J1/00

CPC classification number: G06G7/06

Abstract: An electronic control system for analog circuits has controllable analogue circuits which can be combined with one another by way of an electronic switching network. The digital states of the individual crosspoints of the switching network can be programmed by way of a common switching network. In addition, circuitry is provided for adjusting the operating parameters of the individual analogue circuits and the adjustment is accomplished through the values for the operating parameters being determined in a parameter memory according to a program. Finally, a synchronization of the functional sequence of the programs present in two memories is provided.

Abstract translation: 用于模拟电路的电子控制系统具有可以通过电子交换网络彼此组合的可控模拟电路。 可以通过公共交换网络来编程交换网络的各个交叉点的数字状态。 此外，提供用于调整各个模拟电路的操作参数的电路，并且通过根据程序在参数存储器中确定的操作参数的值来实现调整。 最后，提供存在于两个存储器中的程序的功能序列的同步。

公开(公告)号：US4040082A

公开(公告)日：1977-08-02

申请号：US629394

申请日：1975-11-06

Applicant: Karl Goser

Inventor： Karl Goser

IPC: H01L29/78 ,  G11C11/412 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/085 ,  H01L27/098 ,  H01L27/108 ,  H03K3/3565 ,  H01L27/02

CPC classification number: H03K3/3565 ,  G11C11/412 ,  H01L27/00 ,  H01L27/085 ,  H01L27/098

Abstract: A semiconductor storage arrangement employing a pair of field-effect transistors which are complementary to one another and connected in series, one of the transistors having the source area thereof connected to the gate area of the second transistor and the gate area of the first transistor being connected to the drain area of the second transistor, the drain area of the first transistor being connected to the source area of the second transistor, in which both transistors are disposed on a common semi-conductor substrate and one of the transistors is a junction field-effect transistor, the gate area of which simultaneously forms the source or drain area of the other transistor.