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公开(公告)号:US08828836B2
公开(公告)日:2014-09-09
申请号:US13153626
申请日:2011-06-06
申请人: Karthik Ramani , Hiroyuki Ode , Sandra Malhotra
发明人: Karthik Ramani , Hiroyuki Ode , Sandra Malhotra
摘要: A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal. A dielectric layer is formed over the first electrode. The dielectric layer is subjected to a milliseconds anneal process that serves to crystallize the dielectric material and decrease the concentration of oxygen vacancies.
摘要翻译: 公开了一种用于制造动态随机存取存储器(DRAM)电容器堆叠的方法,其中堆叠包括第一电极,电介质层和第二电极。 第一电极由导电二元金属形成。 在第一电极上形成电介质层。 对电介质层进行几毫秒的退火工艺,以使介电材料结晶并降低氧空位的浓度。
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公开(公告)号:US08765570B2
公开(公告)日:2014-07-01
申请号:US13494808
申请日:2012-06-12
申请人: Sandra Malhotra , Wim Deweerd , Hiroyuki Ode
发明人: Sandra Malhotra , Wim Deweerd , Hiroyuki Ode
IPC分类号: H01L21/20
CPC分类号: H01L28/56 , H01L27/10852 , H01L28/60 , H01L28/90
摘要: A method for forming a capacitor stack is described. In some embodiments of the present invention, a first dielectric material is formed above a first electrode material. The first electrode material is rigid and has good mechanical strength and serves as a robust frame for the capacitor stack. The first dielectric material is sufficiently thin ( 3 nm) or lightly doped or non-doped so that it crystallizes after subsequent anneal treatments. A second electrode material is formed adjacent to the second dielectric material. The second electrode material has a high work function and a crystal structure that serves to promote the formation of the high k-value crystal structure of the second dielectric material.
摘要翻译: 描述形成电容器堆叠的方法。 在本发明的一些实施例中,第一电介质材料形成在第一电极材料之上。 第一电极材料是刚性的并且具有良好的机械强度并且用作用于电容器叠层的坚固框架。 第一介电材料足够薄(<2nm)或高度掺杂,使得在随后的退火处理之后其保持非晶态。 在第一电介质材料上方形成第二电介质材料。 第二介电材料足够厚(> 3nm)或轻掺杂或未掺杂,使得其在随后的退火处理之后结晶。 与第二电介质材料相邻地形成第二电极材料。 第二电极材料具有高功函数和用于促进形成第二电介质材料的高k值晶体结构的晶体结构。
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公开(公告)号:US08574998B2
公开(公告)日:2013-11-05
申请号:US13311368
申请日:2011-12-05
申请人: Sandra Malhotra , Kenichi Koyanagi , Hiroyuki Ode , Xiangxin Rui , Takashi Arao , Naonori Fujiwara
发明人: Sandra Malhotra , Kenichi Koyanagi , Hiroyuki Ode , Xiangxin Rui , Takashi Arao , Naonori Fujiwara
IPC分类号: H01L21/02
CPC分类号: H01L28/40 , H01G4/1272 , H01G4/306 , H01G4/33 , H01L21/02175 , H01L21/02189 , H01L21/02192 , H01L21/02194 , H01L21/022 , H01L21/0228
摘要: A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly or non-doped material. The highly doped material will remain amorphous (
摘要翻译: 用于减少DRAM MIM电容器中的漏电流的方法包括从非晶高掺杂材料,非晶高带隙材料以及轻掺杂或非掺杂材料形成多层电介质叠层。 退火步骤后,高掺杂材料将保持无定形(<30%结晶)。 在退火步骤之后,高带隙材料将保持无定形(<30%结晶)。 在退火步骤之后,轻掺杂或非掺杂材料将变成晶体(> = 30%结晶)。 高带隙材料形成在无定形高掺杂材料和轻掺杂材料和非掺杂材料之间,并提供通过多层电介质叠层的导电的中间屏障。
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公开(公告)号:US08563392B2
公开(公告)日:2013-10-22
申请号:US13310980
申请日:2011-12-05
申请人: Sandra Malhotra , Wim Deweerd , Edward Haywood , Hiroyuki Ode
发明人: Sandra Malhotra , Wim Deweerd , Edward Haywood , Hiroyuki Ode
IPC分类号: H01L21/02
CPC分类号: C23C16/45534 , C23C16/405 , H01L21/28562 , H01L21/32051 , H01L28/60
摘要: In some embodiments of the present invention, methods are developed wherein a gas flow of an electron donating compound (EDC) is introduced in sequence with a precursor pulse and alters the deposition of the precursor material. In some embodiments, the EDC pulse is introduced sequentially with the precursor pulse with a purge step used to remove the non-adsorbed EDC from the process chamber before the precursor is introduced. In some embodiments, the EDC pulse is introduced using a vapor draw technique or a bubbler technique. In some embodiments, the EDC pulse is introduced in the same gas distribution manifold as the precursor pulse. In some embodiments, the EDC pulse is introduced in a separate gas distribution manifold from the precursor pulse.
摘要翻译: 在本发明的一些实施方案中,开发了一种方法,其中给电子化合物(EDC)的气流按前驱脉冲依次导入并改变前体材料的沉积。 在一些实施方案中,EDC脉冲依次与前体脉冲一起引入,其中吹扫步骤用于在引入前体之前从处理室去除未吸附的EDC。 在一些实施例中,使用蒸汽抽吸技术或起泡器技术引入EDC脉冲。 在一些实施例中,EDC脉冲被引入与前驱脉冲相同的气体分配歧管中。 在一些实施例中,EDC脉冲从前驱脉冲引入到单独的气体分配歧管中。
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公开(公告)号:US20130122678A1
公开(公告)日:2013-05-16
申请号:US13294341
申请日:2011-11-11
申请人: Sandra Malhotra , Hanhong Chen , Wim Deweerd , Toshiyuki Hirota , Hiroyuki Ode
发明人: Sandra Malhotra , Hanhong Chen , Wim Deweerd , Toshiyuki Hirota , Hiroyuki Ode
IPC分类号: H01L21/02
CPC分类号: H01L28/60 , C23C16/45534 , H01L21/02175 , H01L21/02178 , H01L21/02186 , H01L21/02189 , H01L21/02194 , H01L21/0228 , H01L27/10852 , H01L28/40 , H01L28/56 , H01L29/4234
摘要: A method for doping a dielectric material by pulsing a first dopant precursor, purging the non-adsorbed precursor, pulsing a second precursor, purging the non-adsorbed precursor, and pulsing a oxidant to form an intermixed layer of two (or more) metal oxide dielectric dopant materials. The method may also be used to form a blocking layer between a bulk dielectric layer and a second electrode layer. The method improves the control of the composition and the control of the uniformity of the dopants throughout the thickness of the doped dielectric material.
摘要翻译: 一种用于通过脉冲第一掺杂剂前体掺杂电介质材料的方法,清洗未吸附的前体,脉冲第二前体,净化未吸附的前体,以及脉冲氧化剂以形成两个(或多个)金属氧化物的混合层 电介质掺杂剂材料。 该方法还可用于在体电介质层和第二电极层之间形成阻挡层。 该方法改善了组合物的控制和掺杂介质材料整个厚度均匀性的控制。
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公开(公告)号:US08440537B1
公开(公告)日:2013-05-14
申请号:US13294341
申请日:2011-11-11
申请人: Sandra Malhotra , Hanhong Chen , Wim Deweerd , Toshiyuki Hirota , Hiroyuki Ode
发明人: Sandra Malhotra , Hanhong Chen , Wim Deweerd , Toshiyuki Hirota , Hiroyuki Ode
IPC分类号: H01L21/20
CPC分类号: H01L28/60 , C23C16/45534 , H01L21/02175 , H01L21/02178 , H01L21/02186 , H01L21/02189 , H01L21/02194 , H01L21/0228 , H01L27/10852 , H01L28/40 , H01L28/56 , H01L29/4234
摘要: A method for doping a dielectric material by pulsing a first dopant precursor, purging the non-adsorbed precursor, pulsing a second precursor, purging the non-adsorbed precursor, and pulsing a oxidant to form an intermixed layer of two (or more) metal oxide dielectric dopant materials. The method may also be used to form a blocking layer between a bulk dielectric layer and a second electrode layer. The method improves the control of the composition and the control of the uniformity of the dopants throughout the thickness of the doped dielectric material.
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公开(公告)号:US08415227B2
公开(公告)日:2013-04-09
申请号:US13220460
申请日:2011-08-29
申请人: Sandra Malhotra , Wim Deweerd , Hanhong Chen , Xiangxin Rui , Hiroyuki Ode , Mitsuhiro Horikawa , Kenichi Koyanagi
发明人: Sandra Malhotra , Wim Deweerd , Hanhong Chen , Xiangxin Rui , Hiroyuki Ode , Mitsuhiro Horikawa , Kenichi Koyanagi
摘要: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.
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公开(公告)号:US20130052792A1
公开(公告)日:2013-02-28
申请号:US13220460
申请日:2011-08-29
申请人: Sandra Malhotra , Wim Deweerd , Hanhong Chen , Xiangxin Rui , Hiroyuki Ode , Mitsuhiro Horikawa , Kenichi Koyanagi
发明人: Sandra Malhotra , Wim Deweerd , Hanhong Chen , Xiangxin Rui , Hiroyuki Ode , Mitsuhiro Horikawa , Kenichi Koyanagi
IPC分类号: H01L21/02
摘要: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.
摘要翻译: 描述了制造DRAM电容器堆叠的方法,其中电介质材料是由与轻掺杂或非掺杂材料组合的高掺杂材料形成的多层叠层。 在退火步骤之后,高掺杂材料保持无定形,结晶含量小于30%。 在退火步骤之后,轻掺杂或非掺杂材料变成结晶含量等于或大于30%的晶体。 电介质多层堆叠保持高的k值,同时使漏电流和EOT值最小化。
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公开(公告)号:US20130122681A1
公开(公告)日:2013-05-16
申请号:US13294309
申请日:2011-11-11
申请人: Sandra Malhotra , Hanhong Chen , Wim Deweerd , Hiroyuki Ode
发明人: Sandra Malhotra , Hanhong Chen , Wim Deweerd , Hiroyuki Ode
IPC分类号: H01L21/02
CPC分类号: H01L28/40 , H01L21/02186 , H01L21/02194 , H01L21/0228 , H01L21/02304 , H01L21/02356 , H01L27/10852 , H01L28/75
摘要: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. A metal oxide second electrode layer is formed above the dielectric layer. The metal oxide second electrode layer has a crystal structure that is compatible with the crystal structure of the dielectric layer. Optionally, a second electrode bulk layer is formed above the metal oxide second electrode layer.
摘要翻译: 用于形成具有低泄漏电流的DRAM MIM电容器堆叠的方法涉及使用用作促进随后沉积的介电层的高k相的模板的第一电极。 高k电介质层包括可在随后的退火处理后结晶的掺杂材料。 金属氧化物第二电极层形成在电介质层的上方。 金属氧化物第二电极层具有与介电层的晶体结构相容的晶体结构。 可选地,在金属氧化物第二电极层上形成第二电极体层。
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公开(公告)号:US20130071987A1
公开(公告)日:2013-03-21
申请号:US13237065
申请日:2011-09-20
申请人: Hanhong Chen , Sandra Malhotra , Wim Deweerd , Hiroyuki Ode
发明人: Hanhong Chen , Sandra Malhotra , Wim Deweerd , Hiroyuki Ode
IPC分类号: H01L21/02
CPC分类号: H01L28/40 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/02194 , H01L21/0228 , H01L27/1085 , H01L28/60
摘要: A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of an compound high k dielectric material. The dielectric material further comprises a dopant. One component of the compound high k dielectric material is present in a concentration between about 30 atomic % and about 80 atomic % and more preferably between about 40 atomic % and about 60 atomic %. In some embodiments, the compound high k dielectric material comprises an alloy of TiO2 and ZrO2 and further comprises a dopant of Al2O3. In some embodiments, the compound high k dielectric material comprises an admixture of TiO2 and HfO2 and further comprises a dopant of Al2O3.
摘要翻译: 用于形成具有低漏电流和低EOT的DRAM MIM电容器堆叠的方法涉及使用复合高k电介质材料。 电介质材料还包括掺杂剂。 复合高k介电材料的一个组分以约30原子%至约80原子%,更优选约40原子%至约60原子%的浓度存在。 在一些实施方案中,化合物高k介电材料包含TiO 2和ZrO 2的合金,并且还包含Al 2 O 3的掺杂剂。 在一些实施方案中,化合物高k介电材料包含TiO 2和HfO 2的混合物,并且还包含Al 2 O 3的掺杂剂。
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