摘要:
A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly or non-doped material. The highly doped material will remain amorphous (
摘要:
A method for fabricating a dynamic random access memory capacitor is disclosed. The method may comprise depositing a first titanium nitride (TiN) electrode; creating a first layer of titanium dioxide (TiO2) on the first TiN electrode; depositing a dielectric material on the first layer of titanium dioxide; and depositing a second TiN electrode on the dielectric material.
摘要:
A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly or non-doped material. The highly doped material will remain amorphous (
摘要:
A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.
摘要:
A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.
摘要:
A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode layer, forming a catalytic layer on the first electrode layer, optionally annealing the catalytic layer, forming a dielectric layer on the catalytic layer, optionally annealing the dielectric layer, forming a second electrode layer on the dielectric layer, and optionally annealing the capacitor stack. Advantageously, the electrode layers are TiN, the catalytic layer is MoO2−x where x is between 0 and 2, and the physical thickness of the catalytic layer is between about 0.5 nm and about 10 nm, and the dielectric layer is ZrO2.
摘要:
A method for processing dielectric materials and electrodes to decrease leakage current is disclosed. The method includes a post dielectric anneal treatment in an oxidizing atmosphere to reduce the concentration of oxygen vacancies in the dielectric material. The method further includes a post metallization anneal treatment in an oxidizing atmosphere to reduce the concentration of interface states at the electrode/dielectric interface and to further reduce the concentration of oxygen vacancies in the dielectric material.
摘要:
A method for processing dielectric materials and electrodes to decrease leakage current is disclosed. The method includes a post dielectric anneal treatment in an oxidizing atmosphere to reduce the concentration of oxygen vacancies in the dielectric material. The method further includes a post metallization anneal treatment in an oxidizing atmosphere to reduce the concentration of interface states at the electrode/dielectric interface and to further reduce the concentration of oxygen vacancies in the dielectric material.
摘要:
A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode layer, forming a catalytic layer on the first electrode layer, optionally annealing the catalytic layer, forming a dielectric layer on the catalytic layer, optionally annealing the dielectric layer, forming a second electrode layer on the dielectric layer, and optionally annealing the capacitor stack. Advantageously, the electrode layers are TiN, the catalytic layer is MoO2−x where x is between 0 and 2, and the physical thickness of the catalytic layer is between about 0.5 nm and about 10 nm, and the dielectric layer is ZrO2.
摘要:
Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact angle of a surface of the metal, and depositing a titanium oxide layer on the exposed metal using at least one of a chemical vapor deposition process and an atomic layer deposition process, wherein the titanium oxide layer comprises at least a portion rutile titanium oxide.