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1.发明授权Circuits and methods for reducing the effects of level shifter delays in systems operating in multiple voltage domains 有权用于减少在多个电压域中工作的系统中电平移位器延迟的影响的电路和方法公开(公告)号：US07348813B1
公开(公告)日：2008-03-25
申请号：US11292523
申请日：2005-12-02
申请人： Kartik Nanda , Aryesh Amar , Rahul Singh , Jerome E Johnston
发明人： Kartik Nanda , Aryesh Amar , Rahul Singh , Jerome E Johnston
IPC分类号： H03L7/00
CPC分类号： H03K19/0175 , H03K19/01
摘要： A method of interfacing circuits operating in different voltage domains includes receiving a first signal with a first circuit operating in a first voltage domain and generating a second signal with a second circuit operating in a second voltage domain. The second signal is level shifted between the first and second voltage domains with a level shifter and synchronized with the first signal with a third circuit operating in the first voltage domain.
摘要翻译： 在不同电压域中操作的电路接口的方法包括：接收具有在第一电压域中工作的第一电路的第一信号，并产生具有在第二电压域中工作的第二电路的第二信号。 第二信号在电平移位器之间在第一和第二电压域之间电平移位，并且与第一信号同步，第三电路在第一电压域中工作。
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2.发明授权Method and system for selecting implementation of a filter controller between a single conversion mode that ensures a fully-settled converted output and a continuous conversion mode 有权用于在确保完全转换的输出和连续转换模式的单个转换模式之间选择滤波器控制器的实现的方法和系统公开(公告)号：US06469650B2
公开(公告)日：2002-10-22
申请号：US09800604
申请日：2001-03-06
申请人： Kartik Nanda , Aryesh Amar , Saibun Wong , Jerome E. Johnston
发明人： Kartik Nanda , Aryesh Amar , Saibun Wong , Jerome E. Johnston
IPC分类号： H03M112
摘要： A method and system for selecting implementation of a filter controller between a single conversion that ensures a fully-settled converted output and a continuous conversion of an input signal are disclosed. State machine determines whether convert start signal has a duration, which ends on or before a first occurrence of a conversion done on the input signal. Conversion done is an occurrence of when a bit set has been converted from the input signal. If convert start signal has a duration which ends on or before the first occurrence of conversion done, then state machine selects and implements single conversion of the input signal. Digital system ensures a fully-settled converted output by waiting for the filter to receive and filter a predetermined number of bit sets for a conversion output and then outputting the conversion output. Otherwise, state machine selects and implements continuous conversion of the input signal.
摘要翻译： 公开了一种用于在确保完全稳定的转换输出和输入信号的连续转换的单个转换之间选择滤波器控制器的实现的方法和系统。 状态机确定转换开始信号是否具有持续时间，其结束于在输入信号上完成的转换的第一次出现之后或之前。 完成的转换是当从输入信号转换位设置时的出现。 如果转换开始信号具有在第一次完成转换之前或之前结束的持续时间，则状态机选择并实现输入信号的单次转换。 数字系统通过等待滤波器接收和过滤用于转换输出的预定数量的位组，然后输出转换输出，确保完全转换的输出。 否则，状态机选择并实现输入信号的连续转换。
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3.发明申请公开(公告)号：US20060125661A1
公开(公告)日：2006-06-15
申请号：US11011983
申请日：2004-12-14
申请人： Kartik Nanda , Aryesh Amar
发明人： Kartik Nanda , Aryesh Amar
IPC分类号： H03M7/00
摘要： Mode selection circuitry selects one of a plurality of operational modes supported by an integrated circuit by detecting a selected connection between a first terminal of the integrated circuit and a mode control terminal of the integrated circuit. Other including a mode control terminal coupled to an integrated circuit for receiving a mode selection signal and mode select circuitry for selecting an operational mode of the integrated circuit in response to a frequency of the mode control signal.
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4.发明授权Circuits and methods for implementing mode selection in multiple-mode integrated circuits 有权用于在多模集成电路中实现模式选择的电路和方法公开(公告)号：US07605723B2
公开(公告)日：2009-10-20
申请号：US11011983
申请日：2004-12-14
申请人： Kartik Nanda , Aryesh Amar
发明人： Kartik Nanda , Aryesh Amar
IPC分类号： H03M7/00
摘要： Mode selection circuitry selects one of a plurality of operational modes supported by an integrated circuit by detecting a selected connection between a first terminal of the integrated circuit and a mode control terminal of the integrated circuit. Other including a mode control terminal coupled to an integrated circuit for receiving a mode selection signal and mode select circuitry for selecting an operational mode of the integrated circuit in response to a frequency of the mode control signal.
摘要翻译： 模式选择电路通过检测集成电路的第一端和集成电路的模式控制端之间的所选连接来选择由集成电路支持的多种操作模式之一。 其他包括耦合到用于接收模式选择信号的集成电路的模式控制终端和用于响应于模式控制信号的频率来选择集成电路的操作模式的模式选择电路。
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5.发明授权公开(公告)号：US07193549B1
公开(公告)日：2007-03-20
申请号：US10891944
申请日：2004-07-15
申请人： Kartik Nanda , Giri Rangan , Aryesh Amar
发明人： Kartik Nanda , Giri Rangan , Aryesh Amar
IPC分类号： H03M1/66
摘要： A method of determining an internal operating mode of an electronic circuit derives multiple comparison rates from a rate of a master clock input, computes one or more clock ratios of the comparison rates to a rate of a sample rate clock input, and determines whether any of the clock ratios is a valid ratio representing a supported clock configuration. The appropriate internal operating mode is then selected based on the valid ratio. In the illustrative embodiment, a clock autodetect unit uses two trip frequencies to derive at least first and second clock comparison rates. The audio converter can operate in three distinct modes (base, high and quad modes). The base mode is selected when the clock ratio is about 256, the high mode is selected when the clock ratio is about 128, and the quad mode is selected when the clock ratio is about 64. A multiplexer can be used to sequence through the computer clock ratios to ensure that a highest valid ratio is used among a plurality of valid ratios.
摘要翻译： 确定电子电路的内部操作模式的方法从主时钟输入的速率导出多个比较速率，计算比较速率的一个或多个时钟比与采样速率时钟输入的速率，并且确定是否有 时钟比率是表示支持的时钟配置的有效比率。 然后根据有效比例选择适当的内部操作模式。 在说明性实施例中，时钟自动检测单元使用两个跳闸频率来导出至少第一和第二时钟比较速率。 音频转换器可以工作在三种不同的模式（基本，高和四模式）。 当时钟比为大约256时选择基本模式，当时钟比为大约128时选择高模式，并且当时钟比为约64时选择四模式。可以使用多路复用器来顺序通过计算机 时钟比，以确保在多个有效比率中使用最高有效比率。
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公开(公告)号：US09563851B2
公开(公告)日：2017-02-07
申请号：US13491212
申请日：2012-06-07
申请人： Jeffrey Bernstein , Benjamin Vigoda , Kartik Nanda , Rishi Chaturvedi , David Hossack , William Peet , Andrew Schweitzer , Timothy Caputo
发明人： Jeffrey Bernstein , Benjamin Vigoda , Kartik Nanda , Rishi Chaturvedi , David Hossack , William Peet , Andrew Schweitzer , Timothy Caputo
摘要： In an aspect, in general, a programmable computation device performs computations of an inference task specified by a plurality of variables and a plurality of factors, each factor being associated with a subset of the variables. The device includes one or more processing elements. Each processing element includes a first storage for a definition of a factor, a second storage for data associated with the inputs and/or outputs of at least some of the computations, and one or more computation units coupled to the first storage and the second storage for performing a succession of parts of the at least some of the computations that are associated with a factor, the succession of parts defined by data in the storage for the definition of the factor.
摘要翻译： 一方面，通常，可编程计算装置执行由多个变量和多个因素指定的推理任务的计算，每个因子与变量的子集相关联。 该装置包括一个或多个处理元件。 每个处理元件包括用于定义因子的第一存储器，用于与至少一些计算的输入和/或输出相关联的数据的第二存储器以及耦合到第一存储器和第二存储器的一个或多个计算单元 用于执行与因素相关联的所述至少一些计算的一部分的连续的部分，所述部分由所述存储器中的数据由所述因子的定义定义的部分所定义。
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公开(公告)号：US20120306569A1
公开(公告)日：2012-12-06
申请号：US13490110
申请日：2012-06-06
申请人： Eric Nestler , Jeffrey Venuti , Vladimir Zlatkovic , Kartik Nanda
发明人： Eric Nestler , Jeffrey Venuti , Vladimir Zlatkovic , Kartik Nanda
IPC分类号： H03K5/00
摘要： An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.
摘要翻译： 时域滤波方法采用无源电荷共享方式来实现无限脉冲响应滤波器。 将输入信号的延迟样本作为电荷存储在第一电容器阵列的电容器上，并且输出信号的延迟采样作为电荷存储在第二电容器阵列的电容器上。 输出由第一和第二阵列的电容器彼此无源耦合确定，并根据耦合的电容器上的总电荷来确定输出。 在一些示例中，在将输出存储在第二电容器阵列之前，将增益应用于总电荷。 在一些示例中，在耦合电容器之前，将电荷量化电路应用于存储在阵列上的电荷以形成输出。
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公开(公告)号：US20090191837A1
公开(公告)日：2009-07-30
申请号：US12241940
申请日：2008-09-30
申请人： Kartik Nanda , John L. Melanson
发明人： Kartik Nanda , John L. Melanson
IPC分类号： H04B1/16
CPC分类号： H02M3/157
摘要： A power control system includes a delta sigma modulator to generate output values for use in controlling a switching power converter. In at least one embodiment, the delta sigma modulator includes two ranges of available output values and a range of one or more unavailable intermediate output values, wherein the range of one or more unavailable intermediate output values represent a gap in available output values. Each unavailable intermediate output value represents an output value that is not generated by the delta sigma modulator. In at least one embodiment, the delta sigma modulator includes a quantizer output remapping module that remaps quantizer output values within the range of one or more unavailable intermediate output values of the delta sigma modulator to new output values within one of the ranges of available output values.
摘要翻译： 功率控制系统包括Δ-Σ调制器以产生用于控制开关功率转换器的输出值。 在至少一个实施例中，ΔΣ调制器包括两个可用输出值范围和一个或多个不可用中间输出值的范围，其中一个或多个不可用中间输出值的范围表示可用输出值中的间隙。 每个不可用的中间输出值表示不由delta-Σ调制器产生的输出值。 在至少一个实施例中，ΔΣ调制器包括量化器输出重映射模块，该量化器输出重映射模块将ΔΣ调制器的一个或多个不可用中间输出值的范围内的量化器输出值重新映射到可用输出值范围内的新输出值 。
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公开(公告)号：US07755525B2
公开(公告)日：2010-07-13
申请号：US12241940
申请日：2008-09-30
申请人： Kartik Nanda , John L. Melanson
发明人： Kartik Nanda , John L. Melanson
IPC分类号： H03M3/00
CPC分类号： H02M3/157
摘要： A power control system includes a delta sigma modulator to generate output values for use in controlling a switching power converter. In at least one embodiment, the delta sigma modulator includes two ranges of available output values and a range of one or more unavailable intermediate output values, wherein the range of one or more unavailable intermediate output values represent a gap in available output values. Each unavailable intermediate output value represents an output value that is not generated by the delta sigma modulator. In at least one embodiment, the delta sigma modulator includes a quantizer output remapping module that remaps quantizer output values within the range of one or more unavailable intermediate output values of the delta sigma modulator to new output values within one of the ranges of available output values.
摘要翻译： 功率控制系统包括Δ-Σ调制器以产生用于控制开关功率转换器的输出值。 在至少一个实施例中，ΔΣ调制器包括两个可用输出值范围和一个或多个不可用中间输出值的范围，其中一个或多个不可用中间输出值的范围表示可用输出值中的间隙。 每个不可用的中间输出值表示不由delta-Σ调制器产生的输出值。 在至少一个实施例中，ΔΣ调制器包括量化器输出重映射模块，该量化器输出重映射模块将ΔΣ调制器的一个或多个不可用中间输出值的范围内的量化器输出值重新映射到可用输出值范围内的新输出值 。
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10.发明授权公开(公告)号：US07750724B2
公开(公告)日：2010-07-06
申请号：US11962022
申请日：2007-12-20
CPC分类号： G05F1/561 , G01R33/0029 , G01R33/07 , G05F3/08
摘要： A temperature and process-stable magnetic field sensor bias current source provides improved performance in Hall effect sensor circuits. A switched-capacitor sensing element is used to sense either a reference current or the bias current directly. A current mirror may be used to generate the bias current from the reference current, and may include multiple current source transistors coupled through corresponding control transistors that are switched using a barrel shifter to reduce variations in the bias current due to process variation. The current mirror control may be provided via a chopper amplifier to reduce flicker noise and the current mirror control voltage may be held using a track/hold circuit during transitions of the chopper amplifier to further reduce noise due to the chopping action.
摘要翻译： 温度和过程稳定的磁场传感器偏置电流源在霍尔效应传感器电路中提供了更好的性能。 开关电容感测元件用于直接感测参考电流或偏置电流。 可以使用电流镜来产生来自参考电流的偏置电流，并且可以包括通过相应的控制晶体管耦合的多个电流源晶体管，所述控制晶体管使用桶形移位器进行切换，以减少由于过程变化引起的偏置电流的变化。 可以经由斩波放大器提供电流镜控制以减少闪烁噪声，并且可以在斩波放大器的转变期间使用轨道/保持电路来保持电流镜控制电压，以进一步减少由于斩波动作引起的噪声。
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