公开(公告)号：US07162506B1

公开(公告)日：2007-01-09

申请号：US11057450

申请日：2005-02-14

申请人： Axel Thomsen ,  Jerome E Johnston ,  Edwin Angel ,  Aryesh Amar

发明人： Axel Thomsen ,  Jerome E Johnston ,  Edwin Angel ,  Aryesh Amar

IPC分类号： G06F17/10

CPC分类号： H03H17/0294 ,  H03M3/392 ,  H03M3/462

摘要： In a signal processing integrated circuit having an analog to digital converter and a digital filter having a plurality of taps separated in time, when starting a conversion after a reset or a change of input channel, the filter will have an incomplete set of input data as the delayed inputs to an output calculation are all zero from the reset operation. After reset, during the time that data are filling up the filter pipeline, the calculation of an output value will give a result that holds information about the input, but does not present the data with the same scaling and frequency content as the fully settled filter. The integrated circuit selectively provides two modes, on that provides only fully settled data from the filter or and another that provides all data from the filter, including unsettled data. Knowledge about the filter coefficients can be utilized by a user or user process to extract information about the input from the unsettled data.

摘要翻译： 在具有模拟数字转换器的信号处理集成电路和具有时间分离的多个抽头的数字滤波器的情况下，当在复位或输入通道改变之后开始转换时，滤波器将具有不完整的输入数据集 输出计算的延迟输入从复位操作全部为零。 在复位之后，在数据填满过滤器管线的时间期间，输出值的计算将给出保存有关输入信息的结果，但不显示具有与完全设置的过滤器相同的缩放和频率内容的数据 。 集成电路有选择地提供两种模式，其中仅提供来自滤波器的完全确定的数据，或者提供来自滤波器的所有数据的另一种模式，包括不稳定的数据。 关于滤波器系数的知识可以由用户或用户进程利用来从未解决的数据中提取关于输入的信息。

公开(公告)号：US06525589B1

公开(公告)日：2003-02-25

申请号：US09695705

申请日：2000-10-25

申请人： Axel Thomsen ,  Edwin De Angel ,  Sherry Wu ,  Aryesh Amar ,  Jerome E. Johnston

发明人： Axel Thomsen ,  Edwin De Angel ,  Sherry Wu ,  Aryesh Amar ,  Jerome E. Johnston

IPC分类号： H03K1716

CPC分类号： H03M3/494 ,  G01D3/022 ,  H03M3/448 ,  H03M3/452

摘要： An instrumentation circuit has an integrated circuit that has input terminals, an amplifier arrangement using feed forward compensation and an analog to digital converter and a serial data output receiving the output from said amplifier arrangement. A bridge circuit, having a transducer, or a thermocouple arrangement are connected to input terminals of the integrated circuit.

摘要翻译： 仪表电路具有具有输入端子的集成电路，使用前馈补偿的放大器装置和模数转换器以及接收来自所述放大器装置的输出的串行数据输出。 具有换能器或热电偶布置的桥式电路连接到集成电路的输入端子。

公开(公告)号：US06469650B2

公开(公告)日：2002-10-22

申请号：US09800604

申请日：2001-03-06

申请人： Kartik Nanda ,  Aryesh Amar ,  Saibun Wong ,  Jerome E. Johnston

发明人： Kartik Nanda ,  Aryesh Amar ,  Saibun Wong ,  Jerome E. Johnston

IPC分类号： H03M112

CPC分类号： H03M3/392 ,  H03M3/474

摘要： A method and system for selecting implementation of a filter controller between a single conversion that ensures a fully-settled converted output and a continuous conversion of an input signal are disclosed. State machine determines whether convert start signal has a duration, which ends on or before a first occurrence of a conversion done on the input signal. Conversion done is an occurrence of when a bit set has been converted from the input signal. If convert start signal has a duration which ends on or before the first occurrence of conversion done, then state machine selects and implements single conversion of the input signal. Digital system ensures a fully-settled converted output by waiting for the filter to receive and filter a predetermined number of bit sets for a conversion output and then outputting the conversion output. Otherwise, state machine selects and implements continuous conversion of the input signal.

摘要翻译： 公开了一种用于在确保完全稳定的转换输出和输入信号的连续转换的单个转换之间选择滤波器控制器的实现的方法和系统。 状态机确定转换开始信号是否具有持续时间，其结束于在输入信号上完成的转换的第一次出现之后或之前。 完成的转换是当从输入信号转换位设置时的出现。 如果转换开始信号具有在第一次完成转换之前或之前结束的持续时间，则状态机选择并实现输入信号的单次转换。 数字系统通过等待滤波器接收和过滤用于转换输出的预定数量的位组，然后输出转换输出，确保完全转换的输出。 否则，状态机选择并实现输入信号的连续转换。

公开(公告)号：US6002355A

公开(公告)日：1999-12-14

申请号：US883364

申请日：1997-06-26

申请人： Bruce Del Signore ,  Qicheng Yu ,  Jerome E. Johnston

发明人： Bruce Del Signore ,  Qicheng Yu ,  Jerome E. Johnston

IPC分类号： H03M1/12 ,  H03M1/00

CPC分类号： H03M1/12

摘要： An analog-to-digital converter (ADC) architecture is fabricated on a semiconductor substrate which is negatively capacitively charge pumped below ground and subject to feedback regulation, rate measurements and adjustments. The ADC receives signal inputs of positive and negative polarity relative to ground, while being powered at 0V and 5V, without any negative power source input, as a result of a closed feedback loop which keeps the negative bias voltage constant as external supplies and component voltages vary. The high frequency pumping of the silicon substrate is subject to timing requirements which permit high resolution analog input signals to be converted in the presence of pump noise.

摘要翻译： 在半导体衬底上制造模数转换器（ADC）架构，其负电容性电荷泵送在地下，并进行反馈调节，速率测量和调整。 由于封闭的反馈环路使得负偏置电压恒定，因此外部电源和分量电压不变，ADC接收到相对于地的正极性和负极性的信号输入，同时在0V和5V电源下没有任何负电源输入 变化。 硅衬底的高频泵浦受到时序要求的限制，允许在存在泵浦噪声的情况下转换高分辨率模拟输入信号。

公开(公告)号：US07215267B1

公开(公告)日：2007-05-08

申请号：US11311611

申请日：2005-12-19

申请人： Jerome E. Johnston

发明人： Jerome E. Johnston

IPC分类号： H03M1/20

CPC分类号： H03M3/328 ,  H03M3/458

摘要： An analog-to-digital converter system comprises an analog-to-digital converter and a dither generator. The analog-to-digital converter receives an analog input signal and generates a digital signal that is proportional to the analog input signal. The output of the analog-to-digital converter is dominated by quantization error. The dither generator is responsive to a user-controlled input for generating an output signal. An adder sums the digital signal from the analog-to-digital converter with the output signal from the dither generator to provide a summed signal. The summed signal is either dominated by quantization noise or is properly dithered depending upon the user-controlled input.

摘要翻译： 模数转换器系统包括模数转换器和抖动发生器。 模数转换器接收模拟输入信号并产生与模拟输入信号成比例的数字信号。 模数转换器的输出由量化误差支配。 抖动发生器响应于用户控制的输入以产生输出信号。 加法器将来自模拟 - 数字转换器的数字信号与来自抖动发生器的输出信号相加，以提供相加的信号。 总和信号由量化噪声支配或根据用户控制输入适当抖动。

公开(公告)号：US4967384A

公开(公告)日：1990-10-30

申请号：US167528

申请日：1988-03-14

申请人： Tommy B. Molinar ,  Jerome E. Johnston

发明人： Tommy B. Molinar ,  Jerome E. Johnston

IPC分类号： G01G19/07 ,  G01G23/37

CPC分类号： G01G19/07 ,  G01G23/3707

摘要： A microprocessor-based system (18) for weighing large objects, such as aircraft, at a number of points is disclosed. A plurality of load sensing units (10) each contain a strain gauges (50), analog amplification and calibration circuits (54), filtering circuits (56, 58), and analog-to-digital conversion circuitry (60). Each of the load sensing units (10) couple through serial data communication channels (14) to a controller (12), which contains a microprocessor (20), a keyboard (46), and a display (36). A microprocessor (20) executes a program which monitors all load sensing units (10), calculates weight based on data obtained from the load sensing units (10) and several compensation factors, and displays weight of a selected load sensing unit (10). Various foreground (200) and keyboard service (300) software routines are discussed.

摘要翻译： 公开了一种基于微处理器的系统（18），其用于在多个点处称重诸如飞机的大型物体。 多个负载感测单元（10）各自包含应变仪（50），模拟放大和校准电路（54），滤波电路（56,58）和模数转换电路（60）。 每个负载感测单元（10）通过串行数据通信信道（14）耦合到包含微处理器（20），键盘（46）和显示器（36）的控制器（12）。 微处理器（20）执行监视所有负载感测单元（10）的程序，基于从负载感测单元（10）获得的数据和多个补偿因子来计算权重，并显示所选择的负载感测单元（10）的权重。 讨论了各种前台（200）和键盘服务（​​300）软件程序。

公开(公告)号：US4836308A

公开(公告)日：1989-06-06

申请号：US177183

申请日：1988-04-04

申请人： Dick E. Davis ,  Charles R. Brazell ,  Jerome E. Johnston

发明人： Dick E. Davis ,  Charles R. Brazell ,  Jerome E. Johnston

IPC分类号： G01G5/06 ,  G01G19/07 ,  G01G23/01

CPC分类号： G01G19/07 ,  G01G23/01 ,  G01G5/06

摘要： A platform weighing system (10) suitable for making accurate weight measurements of heavy objects, such as aircraft, is disclosed. Hardware and software combine to produce the accurate results. Analog hardware (14) includes hydraulic load cells (80a-80d), temperature sensing (91), filtering (90), and voltage-to-frequency conversion (104). Digital hardware (12) receives an oscillation signal output from the voltage-to-frequency conversion (104) and obtains load counts by monitoring the oscillation signal for consistent predetermined durations. The predetermined duration is chosen in software (226) to be immune to particularly pervasive noise signals. A microprocessor (16) converts load counts into a weight code which is output to a display (46). This conversion includes compensation for auto ranging (320), load cell excitation variance (282), temperature compensation (284), null offset variance (286), and zero drifting (304). In addition, nonlinearities in load cell output are compensated by linearly interpolating (288-296) between two of a plurality of calibration points that characterize the load cells (80a-80d ). Such compensations are performed primarily in software (200).

摘要翻译： 公开了一种适用于对飞机等重物进行精确重量测量的平台称重系统（10）。 硬件和软件相结合，产生准确的结果。 模拟硬件（14）包括液压测力传感器（80a-80d），温度感测（91），滤波（90）和电压 - 频率转换（104）。 数字硬件（12）接收从电压 - 频率转换（104）输出的振荡信号，并通过监视振荡信号获得负载计数，以保持一致的预定持续时间。 在软件（226）中选择预定的持续时间以便免受特别普遍的噪声信号的影响。 微处理器（16）将负载计数转换成输出到显示器（46）的权重码。 该转换包括对自动量程（320），称重传感器激励方差（282），温度补偿（284），零偏移方差（286）和零漂移（304）的补偿。 此外，通过在表征称重传感器（80a-80d）的多个校准点中的两个之间进行线性内插（288-296）来补偿称重传感器输出中的非线性。 这种补偿主要在软件（200）中执行。

公开(公告)号：US07348813B1

公开(公告)日：2008-03-25

申请号：US11292523

申请日：2005-12-02

申请人： Kartik Nanda ,  Aryesh Amar ,  Rahul Singh ,  Jerome E Johnston

发明人： Kartik Nanda ,  Aryesh Amar ,  Rahul Singh ,  Jerome E Johnston

IPC分类号： H03L7/00

CPC分类号： H03K19/0175 ,  H03K19/01

摘要： A method of interfacing circuits operating in different voltage domains includes receiving a first signal with a first circuit operating in a first voltage domain and generating a second signal with a second circuit operating in a second voltage domain. The second signal is level shifted between the first and second voltage domains with a level shifter and synchronized with the first signal with a third circuit operating in the first voltage domain.

摘要翻译： 在不同电压域中操作的电路接口的方法包括：接收具有在第一电压域中工作的第一电路的第一信号，并产生具有在第二电压域中工作的第二电路的第二信号。 第二信号在电平移位器之间在第一和第二电压域之间电平移位，并且与第一信号同步，第三电路在第一电压域中工作。

公开(公告)号：US06857002B1

公开(公告)日：2005-02-15

申请号：US09695704

申请日：2000-10-25

申请人： Axel Thomsen ,  Jerome E. Johnston ,  Edwin De Angel ,  Aryesh Amar

发明人： Axel Thomsen ,  Jerome E. Johnston ,  Edwin De Angel ,  Aryesh Amar

IPC分类号： G06F13/00 ,  G06F17/10 ,  H03H17/02 ,  H03M3/02

CPC分类号： H03H17/0294 ,  H03M3/392 ,  H03M3/462

摘要： In a signal processing integrated circuit having an analog to digital converter and a digital filter having a plurality of taps separated in time, when starting a conversion after a reset or a change of input channel, the filter will have an incomplete set of input data as the delayed inputs to an output calculation are all zero from the reset operation. After reset, during the time that data are filling up the filter pipeline, the calculation of an output value will give a result that holds information about the input, but does not present the data with the same scaling and frequency content as the fully settled filter. The integrated circuit selectively provides two modes, on that provides only fully settled data from the filter or and another that provides all data from the filter, including unsettled data. Knowledge about the filter coefficients can be utilized by a user or user process to extract information about the input from the unsettled data.

摘要翻译： 在具有模拟数字转换器的信号处理集成电路和具有时间分离的多个抽头的数字滤波器的情况下，当在复位或输入通道改变之后开始转换时，滤波器将具有不完整的输入数据集 输出计算的延迟输入从复位操作全部为零。 在复位之后，在数据填满过滤器管线的时间期间，输出值的计算将给出保存有关输入信息的结果，但不显示具有与完全设置的过滤器相同的缩放和频率内容的数据 。 集成电路有选择地提供两种模式，其中仅提供来自滤波器的完全确定的数据，或者提供来自滤波器的所有数据的另一种模式，包括不稳定的数据。 关于滤波器系数的知识可以由用户或用户进程利用来从未解决的数据中提取关于输入的信息。

公开(公告)号：US06522274B1

公开(公告)日：2003-02-18

申请号：US09321583

申请日：1999-05-28

申请人： Aryesh Amar ,  Jerome E. Johnston ,  Donald Keith Coffey

发明人： Aryesh Amar ,  Jerome E. Johnston ,  Donald Keith Coffey

IPC分类号： H03M112

CPC分类号： G06F3/05 ,  H03M1/1225

摘要： A method and apparatus are used to process a plurality of analog signals on a corresponding plurality of physical channels using a circuit having analog to digital converter (ADC) components, a serial port interface, and a serial port controller. Logical channel information for one or more logical channels is stored in a register on the serial port controller. Each logical channel specifies one of the physical channels and conversion information. Command bits are set over a serial port input pin, and include at least one pointer bit indicative of a selected logical channel. In response to the command bits, the serial port controller sends signals indicative of the physical channel and the converter property specified in the selected logical channel to the ADC components.

摘要翻译： 一种方法和装置用于使用具有模数转换器（ADC）组件的电路，串行端口接口和串行端口控制器在相应的多个物理信道上处理多个模拟信号。 一个或多个逻辑信道的逻辑信道信息存储在串行端口控制器的寄存器中。 每个逻辑信道指定一个物理信道和转换信息。 命令位通过串行端口输入引脚设置，并且包括指示所选逻辑通道的至少一个指针位。 响应于命令位，串行端口控制器将指示所选逻辑信道中指定的物理信道和转换器特性的信号发送到ADC组件。