公开(公告)号：US5840615A

公开(公告)日：1998-11-24

申请号：US810201

申请日：1997-03-03

申请人： Katsuhiro Aoki ,  Yukio Fukuda ,  Akitoshi Nishimura ,  Tomomi Nagao ,  Shinichi Hachiya

发明人： Katsuhiro Aoki ,  Yukio Fukuda ,  Akitoshi Nishimura ,  Tomomi Nagao ,  Shinichi Hachiya

IPC分类号： C01B13/32 ,  C04B35/49 ,  C23C18/12 ,  H01B3/00 ,  H01G4/12 ,  H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8242

CPC分类号： H01L21/31691 ,  C23C18/1216 ,  C23C18/1254 ,  C23C18/1279 ,  H01L21/02197 ,  H01L21/02282 ,  H01L28/55

摘要： A method for forming a ferroelectric material film, more particularly a lead zirconate titanate (PZT) film by the sol-gel method wherein a lowered oxidative sintering temperature may be adopted in preparing the ferroelectric material film with a perovskite crystalline structure, thereby reducing the risk of oxidation of metal electrodes and other circuits when the ferroelectric material film is employed as a dielectric in semiconductor devices, such as in a capacitor, for example. The method contemplates the preparation of a raw material solution containing an organometallic compound of a metallic element forming the ferroelectric material film, alkanolamine and/or stabilizer comprising a .beta.-diketone, with the concentration of the stabilizer being sufficient to provide a mole ratio to the total metal atoms of (stabilizer/total metal atoms)>3. The method then involves coating the raw material solution, drying the coated raw material solution to form a dried film, and sintering the dried film to form the ferroelectric material film wherein the oxidative sintering is carried out at a relatively low temperature of about 450.degree. C. in forming the ferroelectric material film with a perovskite crystalline structure.

摘要翻译： 通过溶胶 - 凝胶法形成铁电材料膜的方法，特别是锆钛酸铅（PZT）薄膜，其中在制备具有钙钛矿晶体结构的铁电材料膜时可以采用降低的氧化烧结温度，从而降低风险 当将铁电材料膜用作例如电容器等半导体器件中的电介质时，金属电极和其他电路的氧化。 该方法考虑了制备含有形成铁电材料膜的金属元素的有机金属化合物的原料溶液，包含β-二酮的链烷醇胺和/或稳定剂，其稳定剂的浓度足以提供与 （稳定剂/总金属原子）的总金属原子> 3。 然后，该方法包括涂覆原料溶液，干燥涂覆的原料溶液以形成干燥膜，并烧结干燥的膜以形成铁电材料膜，其中氧化烧结在约450℃的较低温度下进行 在形成具有钙钛矿晶体结构的铁电材料膜时。

公开(公告)号：US5654567A

公开(公告)日：1997-08-05

申请号：US724159

申请日：1996-10-01

申请人： Ken Numata ,  Katsuhiro Aoki ,  Yukio Fukuda ,  Akitoshi Nishimura

发明人： Ken Numata ,  Katsuhiro Aoki ,  Yukio Fukuda ,  Akitoshi Nishimura

IPC分类号： H01L21/3205 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L23/52 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/78 ,  H01L23/48 ,  H01L27/02 ,  H01L29/68

CPC分类号： H01L27/11502

摘要： A capacitor, electrode, or wiring structure having an alpha ray emitting source (in particular, a Pt electrode), and an alpha ray shielding layer 18, having at least one type selected from the group of simple metals of nickel, cobalt, copper, and tungsten, their compounds or alloys made of at least two types of these simple metals, and compounds and alloys made of these simple metals and silicon is provided. It is possible to shield off the alpha ray effectively, to suppress generation of soft errors, to enable the use of Pt and other new materials in making the electrodes and wiring, and to reduce the cost of the mold resin.

摘要翻译： 具有α射线发射源（特别是Pt电极）的电容器，电极或布线结构以及具有选自镍，钴，铜等的一类金属的至少一种的α射线屏蔽层18， 提供了由这些简单金属中的至少两种类型制成的钨，它们的化合物或合金，以及由这些简单金属和硅制成的化合物和合金。 可以有效地屏蔽α射线，以抑制软错误的产生，从而能够在制造电极和布线中使用Pt等新材料，并降低模制树脂的成本。

公开(公告)号：US6033953A

公开(公告)日：2000-03-07

申请号：US991132

申请日：1997-12-16

申请人： Katsuhiro Aoki ,  Yukio Fukuda ,  Ken Numata ,  Yasutoshi Okuno ,  Akitoshi Nishimura

发明人： Katsuhiro Aoki ,  Yukio Fukuda ,  Ken Numata ,  Yasutoshi Okuno ,  Akitoshi Nishimura

IPC分类号： H01G4/33 ,  H01L21/02 ,  H01L21/321 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/1085 ,  H01L28/60 ,  H01L21/32115

摘要： A dielectric capacitor is provided which has a reduced leakage current. The surface of a first electrode (38) of the capacitor is electropolished and a dielectric film (40) and a second electrode (37) are successively laminated on it. The convex parts pointed end (38a) existing on the surface of the first electrode is very finely polished uniformly by dissolving according to electropolishing, a spherical curved surface in which the radius of curvature has been enlarged is formed, and the surface of the first electrode is flattened. Therefore, concentration of electrolysis can be prevented during the operation at the interface of the first electrode and the dielectric film, and the leakage current can be reduced considerably.

摘要翻译： 提供了具有减小的漏电流的介质电容器。 对电容器的第一电极（38）的表面进行电解抛光，并在其上依次层压电介质膜（40）和第二电极（37）。 存在于第一电极表面上的凸部尖端（38a）通过电解抛光溶解而形成非常细微的抛光，形成曲面半径扩大的球面曲面，第一电极的表面 扁平化 因此，在第一电极和电介质膜的界面的操作期间可以防止电解浓度，并且可以显着降低泄漏电流。

公开(公告)号：US06721200B2

公开(公告)日：2004-04-13

申请号：US10397909

申请日：2003-03-26

申请人： Akitoshi Nishimura ,  Yukio Fukuda ,  Katsuhiro Aoki

发明人： Akitoshi Nishimura ,  Yukio Fukuda ,  Katsuhiro Aoki

IPC分类号： G11C1122

CPC分类号： G11C11/22 ,  G11C7/14

摘要： A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state. As charge sharing takes place between the bias states of the dummy cells and the shorted bitlines, an averaged reference voltage is produced which is substantially centered between the “0” or “1” states. A sense amplifier receives a sense signal from the target memory cell on an associated bitline, and the averaged reference voltage is received on another bitline input of the sense amplifier. Thus, a new ferroelectric memory structure provides a centered reference voltage and a simple sensing scheme for the accurate sensing of the logic state of an FeRAM 1T1C cell for a read operation.

公开(公告)号：US06297085B1

公开(公告)日：2001-10-02

申请号：US08988687

申请日：1997-12-11

申请人： Katsuhiro Aoki ,  Yukio Fukuda ,  Ikuko Murayama ,  Ken Numata ,  Akitoshi Nishimura

发明人： Katsuhiro Aoki ,  Yukio Fukuda ,  Ikuko Murayama ,  Ken Numata ,  Akitoshi Nishimura

IPC分类号： H01L218242

CPC分类号： H01L27/11502 ,  H01L21/02197 ,  H01L21/02266 ,  H01L21/31691 ,  H01L27/1085 ,  H01L28/56

摘要： To provide a method that can be used to form a high-qualility ferroelectric film by forming good nuclei when using the sputtering method to manufacture a PZT capacitor or other forroelectric capacitors using Ir or other electrode substances in addition to Pt for the electrode. In the method for manufacturing a PZT ferroelectric capacitor CAP, after titanium film 31 is deposited on Ir electrode 6, lead oxide 32 is deposited at a substrate temperature higher than the crystallization temperature of lead titanate using the sputtering method. Lead zirconate titanate 34 is then deposited at a substrate temperature higher than the aforementioned substrate temperature using the sputtering temperature. Afterwards, a heat treatment of the deposited film is performed to produce PZT film 17.

摘要翻译： 为了提供一种方法，当使用溅射方法制造PZT电容器或使用Ir或其它电极物质的其它电介质电容器或除电极用Pt之外的其他电介质电容器时，可以通过形成良好的核来形成高质量铁电体膜。 在制造PZT铁电体电容器CAP的方法中，在氧化钛电极6上沉积钛膜31之后，使用溅射法在高于钛酸铅的结晶温度的衬底温度下沉积氧化铅32。 然后使用溅射温度在高于上述衬底温度的衬底温度下沉积锆钛酸铅34。 然后，进行沉积膜的热处理以产生PZT膜17。

公开(公告)号：US6150183A

公开(公告)日：2000-11-21

申请号：US993873

申请日：1997-12-18

申请人： Yukio Fukuda ,  Katsuhiro Aoki ,  Akitoshi Nishimura ,  Ken Numata

发明人： Yukio Fukuda ,  Katsuhiro Aoki ,  Akitoshi Nishimura ,  Ken Numata

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01G7/06

CPC分类号： H01L21/02197 ,  H01L21/02266 ,  H01L21/31691 ,  H01L28/55

摘要： A metal oxide capacitor is manufactured by sequentially laminating a metal oxide film and a secon electrode on a first electrode. The metal oxide film is formed and then heat-treated in an atmosphere with an oxygen pressure higher than 1 atm.

摘要翻译： 通过在第一电极上依次层叠金属氧化物膜和第二电极来制造金属氧化物电容器。 形成金属氧化物膜，然后在氧气压力高于1atm的气氛中进行热处理。

公开(公告)号：US06728128B2

公开(公告)日：2004-04-27

申请号：US10397878

申请日：2003-03-26

申请人： Akitoshi Nishimura ,  Yukio Fukuda ,  Katsuhiro Aoki

发明人： Akitoshi Nishimura ,  Yukio Fukuda ,  Katsuhiro Aoki

IPC分类号： G11C1122

CPC分类号： G11C11/22 ,  G11C7/14

摘要： A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state. As charge sharing takes place between the bias states of the dummy cells and the shorted bitlines, an averaged reference voltage is produced which is substantially centered between the “0” or “1” states. A sense amplifier receives a sense signal from the target memory cell on an associated bitline, and the averaged reference voltage is received on another bitline input of the sense amplifier. Thus, a new ferroelectric memory structure provides a centered reference voltage and a simple sensing scheme for the accurate sensing of the logic state of an FeRAM 1T1C cell for a read operation.

摘要翻译： 对于FeRAM存储器件应用的铁电电容器单元阵列中的1T1C布置描述了铁电存储器结构。 器件结构为读取FeRAM阵列的目标存储单元的状态的读出放大器提供精确的参考电压和简单的感测方案。 参考电路产生参考电压，其是在多个FeRAM虚拟单元之间共享的电荷的函数。 多个FeRAM虚拟单元中的每个虚拟单元选择性地耦合到多个位线。 参考电路中的短路晶体管将与所选择的目标存储器单元相邻的两个位线或两个位线条耦合。 一个虚拟单元耦合到两个短路位线或位线条中的选择一个，另一个虚设单元耦合到两个短路位线或位线条中的另一个，其中至少一个虚设单元偏置为“0” “状态，并且至少一个其他虚拟单元被偏置到”1“状态。 由于在虚设单元的偏置状态和短路位线之间发生电荷共享，产生基本上以“0”或“1”状态为中心的平均参考电压。 感测放大器在相关联的位线上接收来自目标存储器单元的感测信号，并且平均参考电压在读出放大器的另一位线输入端上被接收。 因此，新的铁电存储器结构提供了居中的参考电压和用于精确检测用于读取操作的FeRAM 1T1C单元的逻辑状态的简单感测方案。

公开(公告)号：US06724646B2

公开(公告)日：2004-04-20

申请号：US10397409

申请日：2003-03-26

申请人： Akitoshi Nishimura ,  Yukio Fukuda ,  Katsuhiro Aoki

发明人： Akitoshi Nishimura ,  Yukio Fukuda ,  Katsuhiro Aoki

IPC分类号： G11C1122

CPC分类号： G11C11/22 ,  G11C7/14

摘要： A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state. As charge sharing takes place between the bias states of the dummy cells and the shorted bitlines, an averaged reference voltage is produced which is substantially centered between the “0” or “1” states. A sense amplifier receives a sense signal from the target memory cell on an associated bitline, and the averaged reference voltage is received on another bitline input of the sense amplifier. Thus, a new ferroelectric memory structure provides a centered reference voltage and a simple sensing scheme for the accurate sensing of the logic state of an FeRAM 1T1C cell for a read operation.

公开(公告)号：US06587367B1

公开(公告)日：2003-07-01

申请号：US10102418

申请日：2002-03-19

申请人： Akitoshi Nishimura ,  Yukio Fukuda ,  Katsuhiro Aoki

发明人： Akitoshi Nishimura ,  Yukio Fukuda ,  Katsuhiro Aoki

IPC分类号： G11C1122

CPC分类号： G11C11/22 ,  G11C7/14

摘要： A ferroelectric memory structure is described for the 1T1C arrangement in ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state. As charge sharing takes place between the bias states of the dummy cells and the shorted bitlines, an averaged reference voltage is produced which is substantially centered between the “0” or “1” states. A sense amplifier receives a sense signal from the target memory cell on an associated bitline, and the averaged reference voltage is received on another bitline input of the sense amplifier. Thus, a new ferroelectric memory structure provides a centered reference voltage and a simple sensing scheme for the accurate sensing of the logic state of an FeRAM 1T1C cell for a read operation.

摘要翻译： 铁电存储器结构描述了用于FeRAM存储器件应用的铁电电容器阵列中的1T1C布置。 器件结构为读取FeRAM阵列的目标存储单元的状态的读出放大器提供精确的参考电压和简单的感测方案。 参考电路产生参考电压，其是在多个FeRAM虚拟单元之间共享的电荷的函数。 多个FeRAM虚拟单元中的每个虚拟单元选择性地耦合到多个位线。 参考电路中的短路晶体管将与所选择的目标存储器单元相邻的两个位线或两个位线条耦合。 一个虚拟单元耦合到两个短路位线或位线条中的选择一个，另一个虚设单元耦合到两个短路位线或位线条中的另一个，其中至少一个虚设单元偏置为“0” “状态，并且至少一个其他虚拟单元被偏置到”1“状态。 由于在虚设单元的偏置状态和短路位线之间发生电荷共享，产生基本上以“0”或“1”状态为中心的平均参考电压。 感测放大器在相关联的位线上接收来自目标存储器单元的感测信号，并且平均参考电压在读出放大器的另一位线输入端上被接收。 因此，新的铁电存储器结构提供了居中的参考电压和用于精确检测用于读取操作的FeRAM 1T1C单元的逻辑状态的简单感测方案。

公开(公告)号：US5793600A

公开(公告)日：1998-08-11

申请号：US545980

申请日：1995-10-20

申请人： Yukio Fukuda ,  Katsuhiro Aoki ,  Akitoshi Nishimura ,  Ken Numata

发明人： Yukio Fukuda ,  Katsuhiro Aoki ,  Akitoshi Nishimura ,  Ken Numata

IPC分类号： H01L21/02 ,  H01G4/06 ,  H01G7/00

CPC分类号： H01L28/75 ,  H01L28/60 ,  H01L28/55 ,  Y10T29/435

摘要： A capacitor and electrode structure comprising a PZT ferroelectric layer 17 with a primary component (Pb) and secondary component (Ti), a lower electrode layer 16 formed on the underside of the ferroelectric layer and made up of a special element (Pt) and Ti, and compounds thereof, and a diffusion barrier layer 18 which is formed on the underside of the lower electrode layer and which functions as a diffusion barrier with respect to Pb. The capacitor and the electrode structure, which may be a component of a semiconductor memory device, suppress fluctuations in the composition of the ferroelectric layer in PZT, etc., so as to maintain the intended performance of the PZT ferroelectric layer, thereby simplifying and stabilizing film fabrication, and preventing the degradation of electrical characteristics and adverse effects on lower layers.

摘要翻译： 包括具有主要组分（Pb）和次要组分（Ti）的PZT铁电层17的电容器和电极结构，形成在铁电层的下侧上并由特殊元素（Pt）和Ti构成的下电极层16 ，及其化合物，以及扩散阻挡层18，其形成在下电极层的下侧，并且用作相对于Pb的扩散阻挡层。 可以是半导体存储器件的组件的电容器和电极结构抑制PZT等中的铁电层的组成的波动，以保持PZT铁电层的预期性能，从而简化和稳定 薄膜制造，并防止电气特性的劣化和对较低层的不利影响。