公开(公告)号：US20110209107A1

公开(公告)日：2011-08-25

申请号：US13028525

申请日：2011-02-16

申请人： Katsuyoshi KODERA ,  Chikaaki Kodama

发明人： Katsuyoshi KODERA ,  Chikaaki Kodama

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： According to one embodiment, a design layout highly likely to be a dangerous point in a lithography process is set, a coherence map kernel for generating the mask layout is set with respect to the set design layout, the coherence map is created based on the set coherence map kernel and the set design layout, the auxiliary pattern is extracted from the created coherence map and shaped to generate the mask layout, a cost function COST for evaluating an optimization degree of the mask layout is defined, the generated mask layout is evaluated using the cost function, and at least one of parameters of the coherence map kernel and parameters in extracting and shaping the auxiliary pattern from the coherence map are changed until the mask layout evaluated using the cost function is optimized.

摘要翻译： 根据一个实施例，设置在光刻过程中很可能是危险点的设计布局，相对于集合设计布局设置用于生成掩模布局的相干映射内核，基于该集合创建相干映射 相干映射内核和集合设计布局，从创建的相干图中提取辅助模式并对其进行整形以生成掩模布局，定义用于评估掩模布局优化度的成本函数COST，使用 成本函数以及从相干图提取和整形辅助图案中的相干图核心和参数中的至少一个被改变，直到使用成本函数评估的掩模布局被优化为止。

公开(公告)号：US08336006B2

公开(公告)日：2012-12-18

申请号：US13028525

申请日：2011-02-16

申请人： Katsuyoshi Kodera ,  Chikaaki Kodama

发明人： Katsuyoshi Kodera ,  Chikaaki Kodama

IPC分类号： G06F17/50 ,  G03H3/00

CPC分类号： G06F17/5068

摘要： According to one embodiment, a design layout highly likely to be a dangerous point in a lithography process is set, a coherence map kernel for generating the mask layout is set with respect to the set design layout, the coherence map is created based on the set coherence map kernel and the set design layout, the auxiliary pattern is extracted from the created coherence map and shaped to generate the mask layout, a cost function COST for evaluating an optimization degree of the mask layout is defined, the generated mask layout is evaluated using the cost function, and at least one of parameters of the coherence map kernel and parameters in extracting and shaping the auxiliary pattern from the coherence map are changed until the mask layout evaluated using the cost function is optimized.

摘要翻译： 根据一个实施例，设置在光刻过程中很可能是危险点的设计布局，相对于集合设计布局设置用于生成掩模布局的相干映射内核，基于该集合创建相干映射 相干映射内核和集合设计布局，从创建的相干图中提取辅助模式并对其进行整形以生成掩模布局，定义用于评估掩模布局优化度的成本函数COST，使用 成本函数以及从相干图提取和整形辅助图案中的相干图核心和参数中的至少一个被改变，直到使用成本函数评估的掩模布局被优化为止。

公开(公告)号：US08617999B2

公开(公告)日：2013-12-31

申请号：US13397750

申请日：2012-02-16

申请人： Hiromitsu Mashita ,  Toshiya Kotani ,  Fumiharu Nakajima ,  Takafumi Taguchi ,  Chikaaki Kodama

发明人： Hiromitsu Mashita ,  Toshiya Kotani ,  Fumiharu Nakajima ,  Takafumi Taguchi ,  Chikaaki Kodama

IPC分类号： H01L21/302

CPC分类号： H01L21/0337

摘要： A method of manufacturing a semiconductor device, which forms a pattern by performing pattern transformation steps multiple times, comprises setting finished pattern sizes for patterns to be formed in each consecutive two pattern transformation steps among the plurality of pattern transformation steps based on a possible total amount of in-plane size variation of the patterns to be formed in the consecutive two pattern transformation steps.

摘要翻译： 通过多次执行图案变换步骤来形成图案的半导体器件的制造方法包括：在多个图案变换步骤中，基于可能的总量，在每个连续的两个图案变换步骤中设定要形成的图案的完成图案尺寸 在连续的两个图案变换步骤中要形成的图案的平面尺寸变化。

公开(公告)号：US20120311511A1

公开(公告)日：2012-12-06

申请号：US13399042

申请日：2012-02-17

申请人： Takafumi TAGUCHI ,  Toshiya Kotani ,  Chikaaki Kodama ,  Fumiharu Nakajima

发明人： Takafumi TAGUCHI ,  Toshiya Kotani ,  Chikaaki Kodama ,  Fumiharu Nakajima

IPC分类号： G06F17/50

CPC分类号： G03F1/36 ,  G03F1/70 ,  G06F17/5009

摘要： A mask inspection method according to the embodiments, original data corresponding to a semiconductor integrated circuit pattern to be formed on a substrate is created. After that, original production simulation which mocks an original production process is performed on the original data to derive information relating to an original pattern shape in the case of forming an original pattern corresponding to the original data on an original. After that, whether or not the information relating to an original pattern shape satisfies a predetermined value decided based on the original production process is determined.

摘要翻译： 根据实施例的掩模检查方法，产生对应于要形成在基板上的半导体集成电路图案的原始数据。 之后，对原始数据执行原始制作过程的原始制作模拟，以在形成与原始数据相对应的原始图案的情况下导出与原始图案形状有关的信息。 之后，确定与原始图案形状相关的信息是否满足基于原始制作处理决定的预定值。

公开(公告)号：US08298928B2

公开(公告)日：2012-10-30

申请号：US12332788

申请日：2008-12-11

申请人： Kosuke Yanagidaira ,  Chikaaki Kodama

发明人： Kosuke Yanagidaira ,  Chikaaki Kodama

IPC分类号： H01L21/44

CPC分类号： H01L23/528 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/48 ,  H01L23/522 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.

摘要翻译： 本发明的一个实施例的半导体器件的制造方法包括：在衬底上形成待加工的绝缘层; 在所述衬底上的第一区域中形成第一牺牲层，所述第一牺牲层被图案化以在所述第一区域中形成连接到元件的功能线; 在所述衬底上的第二区域中形成第二牺牲层，所述第二牺牲层被图案化以在所述第二区域中形成虚拟布线; 在所述第一牺牲层的侧壁处形成第三牺牲层，并在所述第二牺牲层的侧壁处形成第四牺牲层，所述第三牺牲层和所述第四牺牲层被分离; 通过使用第三牺牲层和第四牺牲层作为掩模蚀刻待处理的绝缘层来形成凹部; 并在凹部中填充导电材料。

公开(公告)号：US20100081265A1

公开(公告)日：2010-04-01

申请号：US12557111

申请日：2009-09-10

申请人： Hiromitsu Mashita ,  Toshiya Kotani ,  Hidefumi Mukai ,  Fumiharu Nakajima ,  Chikaaki Kodama

发明人： Hiromitsu Mashita ,  Toshiya Kotani ,  Hidefumi Mukai ,  Fumiharu Nakajima ,  Chikaaki Kodama

IPC分类号： H01L21/28

CPC分类号： H01L27/11524 ,  H01L21/0337 ,  H01L21/32139

摘要： According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a first film on a target film; forming resist patterns on the first film; processing the first film with the resist patterns to form first patterns including: periodic patterns; and aperiodic patterns; removing the resist patterns; forming a second film over the target film; processing the second film to form second side wall patterns on side walls of the first patterns; removing the periodic patterns; and processing the target film with the aperiodic patterns and the second side wall patterns, thereby forming a target patterns including: periodic target patterns; aperiodic target patterns; and dummy patterns arranged between the periodic target patterns and the aperiodic patterns and arranged periodically with the periodic target patterns.

摘要翻译： 根据本发明的一个方面，提供一种制造半导体器件的方法，所述方法包括：在靶膜上形成第一膜; 在第一膜上形成抗蚀剂图案; 用抗蚀剂图案处理第一膜以形成第一图案，包括：周期图案; 和非周期性模式; 去除抗蚀剂图案; 在目标膜上形成第二膜; 处理所述第二膜以在所述第一图案的侧壁上形成第二侧壁图案; 去除周期性模式; 用非周期图案和第二侧壁图案处理目标薄膜，从而形成包括周期性目标图案的目标图案; 非周期目标模式; 以及布置在周期性目标图案和非周期性图案之间的虚拟图案，并且周期性地布置有周期性目标图案。

公开(公告)号：US20050005252A1

公开(公告)日：2005-01-06

申请号：US10805478

申请日：2004-03-22

申请人： Chikaaki Kodama ,  Akiihiro Yoshitake

发明人： Chikaaki Kodama ,  Akiihiro Yoshitake

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5081

摘要： An edge extraction unit extracts vertical and horizontal wiring edges and slanted wiring edges from overall wiring graphics, and a wiring width classification unit executes a scaling process for the overall wiring graphics to classify the wiring graphics into wiring width ranges which are divided by a predefined reference wiring width. A vertical and horizontal wiring edge extraction unit extracts the vertical and horizontal wiring edges which are in contact with graphics classified into the wiring width ranges, and a vertical and horizontal wiring interval verification unit verifies intervals between the vertical and horizontal wiring edges and opposed edges to be verification counterparts based on a vertical and horizontal reference interval for each wiring width range. A slanted wiring edge extraction unit extracts slanted wiring edges which are in contact with graphics classified into the wiring width ranges, and a slanted wiring interval verification unit verifies intervals between the slanted wiring edges and opposed edges to be verification counterparts based on a slanted reference interval for each wiring width range.

摘要翻译： 边缘提取单元从整体布线图形中提取垂直和水平布线边缘和倾斜的布线边缘，并且布线宽度分类单元执行整个布线图形的缩放处理以将布线图形分类为由预定义的参考划分的布线宽度范围 接线宽度。 垂直和水平布线边缘提取单元提取与分类为布线宽度范围的图形接触的垂直和水平布线边缘，并且垂直和水平布线间隔验证单元验证垂直和水平布线边缘和相对边缘之间的间隔，以 基于每个布线宽度范围的垂直和水平参考间隔的验证对象。 倾斜的布线边缘提取单元提取与分类为布线宽度范围的图形相接触的倾斜布线边缘，并且倾斜布线间隔验证单元基于倾斜的参考间隔来验证倾斜的布线边缘和相对的边缘之间的间隔作为验证对象 对于每个接线宽度范围。

公开(公告)号：US08809072B2

公开(公告)日：2014-08-19

申请号：US13051961

申请日：2011-03-18

申请人： Chikaaki Kodama ,  Toshiya Kotani ,  Shigeki Nojima ,  Shoji Mimotogi

发明人： Chikaaki Kodama ,  Toshiya Kotani ,  Shigeki Nojima ,  Shoji Mimotogi

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： G03F1/36

摘要： According to a sub-resolution assist feature arranging method in embodiments, it is selected which of a rule base and a model base is set for which pattern region on pattern data corresponding to a main pattern as a type of the method of arranging the sub-resolution assist feature for improving resolution of the main pattern formed on a substrate. Then, the sub-resolution assist feature by the rule base is arranged in a pattern region set as the rule base and the sub-resolution assist feature by the model base is arranged in a pattern region set as the model base.

摘要翻译： 根据实施例中的子分辨率辅助特征排列方法，选择规则库和模型库中的哪一个被设置为对应于主图案的图案数据上的哪个图案区域作为安排子图形的方法的类型， 分辨率辅助功能，用于提高在基板上形成的主图案的分辨率。 然后，将规则库的子分辨率辅助特征设置在设置为规则库的图案区域中，并且由模型库将子分辨率辅助特征排列在设置为模型库的图案区域中。

公开(公告)号：US20120241834A1

公开(公告)日：2012-09-27

申请号：US13234052

申请日：2011-09-15

申请人： Fumiharu Nakajima ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Takafumi Taguchi ,  Ryota Aburada ,  Chikaaki Kodama

发明人： Fumiharu Nakajima ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Takafumi Taguchi ,  Ryota Aburada ,  Chikaaki Kodama

IPC分类号： H01L27/088 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/768 ,  H01L21/76816 ,  H01L27/0688 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578

摘要： According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1)th second sidewall film matching a pattern of a nth (where n is an integer of 1 or more) first sidewall film on a lateral surface of a sacrificial layer. A first dimension matching an interconnect width of the interconnects and an interconnects interval in the element formation area is (k1/2n)×(λ/NA) or less when an exposure wavelength of an exposure device is λ, a numerical aperture of a lens of the exposure device is NA and a process parameter is k1. A second dimension matching an interconnect interval in the drawing area is greater than the first dimension.

摘要翻译： 根据一个实施例，半导体器件包括从元件形成区域延伸到绘图区域并且与元件形成区域中的半导体元件连接并且与绘图区域中的触点连接的互连。 基于在牺牲层的侧表面上匹配第n个（其中n是1或更大的整数）的第一侧壁膜的图案的第（n + 1）第二侧壁膜的图案形成互连。 当曝光装置的曝光波长为λ时，在元件形成区域中匹配互连的互连宽度的第一尺寸和元件形成区域中的互连间隔为（k1 / 2n）×（λ/ NA）或更小，透镜的数值孔径 的曝光装置为NA，处理参数为k1。 在绘图区域中匹配互连间隔的第二维大于第一维度。

公开(公告)号：US08143171B2

公开(公告)日：2012-03-27

申请号：US12403740

申请日：2009-03-13

申请人： Hiromitsu Mashita ,  Toshiya Kotani ,  Fumiharu Nakajima ,  Takafumi Taguchi ,  Chikaaki Kodama

发明人： Hiromitsu Mashita ,  Toshiya Kotani ,  Fumiharu Nakajima ,  Takafumi Taguchi ,  Chikaaki Kodama

IPC分类号： H01L21/461

CPC分类号： H01L21/0337

摘要： A method of manufacturing a semiconductor device, which forms a pattern by performing pattern transformation steps multiple times, comprises setting finished pattern sizes for patterns to be formed in each consecutive two pattern transformation steps among the plurality of pattern transformation steps based on a possible total amount of in-plane size variation of the patterns to be formed in the consecutive two pattern transformation steps.

摘要翻译： 通过多次执行图案变换步骤来形成图案的半导体器件的制造方法包括：在多个图案变换步骤中，基于可能的总量，在每个连续的两个图案变换步骤中设定要形成的图案的完成图案尺寸 在连续的两个图案变换步骤中要形成的图案的平面尺寸变化。