公开(公告)号：US20100118636A1

公开(公告)日：2010-05-13

申请号：US12688254

申请日：2010-01-15

申请人： Kaushik Chanda ,  Lynne M. Gignac ,  Wai-Kin Li ,  Ping-Chuan Wang

发明人： Kaushik Chanda ,  Lynne M. Gignac ,  Wai-Kin Li ,  Ping-Chuan Wang

IPC分类号： G11C17/16 ,  H01L23/525 ,  H01L21/44

CPC分类号： G11C17/16 ,  H01L21/7682 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.

摘要翻译： 一种电可重新编程的保险丝，其包括设置在电介质材料中的互连，布置在所述互连的第一端的感测线，布置在所述互连的第二端的第一编程线，以及设置在所述互连的第二端的第二编程线 其中当从所述第一编程线通过所述互连件施加第一定向电子线到所述第二编程线时，所述保险丝可操作以在所述互连和感测线之间的界面处形成表面空隙，并且其中，所述保险丝是 当从所述第二编程线通过所述互连件施加第二编程线到所述第一编程线时，还可操作以治愈所述互连和所述感测线之间的表面空隙。

公开(公告)号：US20090045484A1

公开(公告)日：2009-02-19

申请号：US11839716

申请日：2007-08-16

申请人： Kaushik Chanda ,  Lynne M. Gignac ,  Wai-Kin Li ,  Ping-Chuan Wang

发明人： Kaushik Chanda ,  Lynne M. Gignac ,  Wai-Kin Li ,  Ping-Chuan Wang

IPC分类号： H01L23/52 ,  H01H37/76 ,  H01L23/525 ,  H01L21/44 ,  H01L29/00

CPC分类号： G11C17/16 ,  H01L21/7682 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.

摘要翻译： 一种电可重新编程的保险丝，其包括设置在电介质材料中的互连，布置在所述互连的第一端的感测线，布置在所述互连的第二端的第一编程线，以及设置在所述互连的第二端的第二编程线 其中当从所述第一编程线通过所述互连件施加第一定向电子线到所述第二编程线时，所述保险丝可操作以在所述互连和感测线之间的界面处形成表面空隙，并且其中，所述保险丝是 当从所述第二编程线通过所述互连件施加第二编程线到所述第一编程线时，还可操作以治愈所述互连和所述感测线之间的表面空隙。

公开(公告)号：US08535991B2

公开(公告)日：2013-09-17

申请号：US12688254

申请日：2010-01-15

申请人： Kaushik Chanda ,  Lynne M. Gignac ,  Wai-Kin Li ,  Ping-Chuan Wang

发明人： Kaushik Chanda ,  Lynne M. Gignac ,  Wai-Kin Li ,  Ping-Chuan Wang

IPC分类号： H01L21/82

CPC分类号： G11C17/16 ,  H01L21/7682 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.

摘要翻译： 一种电可重新编程的保险丝，其包括设置在电介质材料中的互连，布置在所述互连的第一端的感测线，布置在所述互连的第二端的第一编程线，以及设置在所述互连的第二端的第二编程线 其中当从所述第一编程线通过所述互连件施加第一定向电子线到所述第二编程线时，所述保险丝可操作以在所述互连和感测线之间的界面处形成表面空隙，并且其中，所述保险丝是 当从所述第二编程线通过所述互连件施加第二编程线到所述第一编程线时，还可操作以治愈所述互连和所述感测线之间的表面空隙。

公开(公告)号：US20080303164A1

公开(公告)日：2008-12-11

申请号：US11758206

申请日：2007-06-05

申请人： Kaushik Chandra ,  Ronald G. Filippi ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Chih-Chao Yang

发明人： Kaushik Chandra ,  Ronald G. Filippi ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Chih-Chao Yang

IPC分类号： H01L23/52 ,  H01L21/44

CPC分类号： H01L23/528 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer.

摘要翻译： 用于减少半导体器件中的电迁移破裂和挤出效应的结构包括形成在第一介电层中的第一金属线; 形成在第一金属线和第一介电层上的盖层; 形成在所述盖层上的第二电介质层; 以及形成在第二介电层中的空隙，停止在盖层上，其中，空隙以如下方式定位，以便隔离由于第一金属线的电迁移效应引起的结构损坏，包括一种或多种金属挤压的效果 来自第一金属线的材料和帽层相对于第一介电层分层的裂纹。

公开(公告)号：US20120264295A1

公开(公告)日：2012-10-18

申请号：US13530999

申请日：2012-06-22

申请人： Kaushik Chandra ,  Ronald G. Filippi ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Chih-Chao Yang

发明人： Kaushik Chandra ,  Ronald G. Filippi ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Chih-Chao Yang

IPC分类号： H01L21/44

CPC分类号： H01L23/528 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer.

摘要翻译： 用于减少半导体器件中的电迁移破裂和挤出效应的结构包括形成在第一介电层中的第一金属线; 形成在第一金属线和第一介电层上的盖层; 形成在所述盖层上的第二电介质层; 以及形成在所述第二介电层中的空隙，停止在所述盖层上，其中所述空隙以这样的方式定位，以便隔离由于所述第一金属线的电迁移效应引起的结构损坏，所述效果包括一种或多种金属挤压 来自第一金属线的材料和帽层相对于第一介电层分层的裂纹。

公开(公告)号：US07671444B2

公开(公告)日：2010-03-02

申请号：US11767580

申请日：2007-06-25

申请人： Ping-Chuan Wang ,  Wai-Kin Li

发明人： Ping-Chuan Wang ,  Wai-Kin Li

IPC分类号： H01L23/525 ,  H01L23/58 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to an e-fuse device including an opening, a first via and a second via in an interlayer dielectric, wherein the opening, the first via and the second via are connected to an interconnect below the interlayer dielectric; a dielectric layer that encloses the first via and the second via; and a metal layer over the dielectric layer, wherein the metal layer fills the opening with a metal, and wherein the first via and the second via are substantially empty to allow for electromigration of the interconnect during re-programming of the e-fuse device.

摘要翻译： 本公开总体上涉及集成电路（IC）芯片制造，更具体地，涉及包括开口，层间电介质中的第一通孔和第二通孔的电熔丝装置，其中开口，第一通孔和第二通孔 连接到层间电介质下面的互连; 包围第一通孔和第二通孔的电介质层; 以及在所述介电层上的金属层，其中所述金属层用金属填充所述开口，并且其中所述第一通孔和所述第二通孔基本为空，以允许在所述电熔丝装置的重新编程期间所述互连件的电迁移。

公开(公告)号：US09331012B2

公开(公告)日：2016-05-03

申请号：US13414825

申请日：2012-03-08

申请人： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian Yang

发明人： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian Yang

IPC分类号： H01K3/10 ,  H01L23/522 ,  H01L23/528 ,  H04L9/32 ,  H05K1/02

CPC分类号： H01L23/5222 ,  H01L21/0274 ,  H01L21/3212 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H04L9/3278 ,  H04L2209/12 ,  H05K1/0289 ,  Y10T29/49117 ,  Y10T29/49165 ,  H01L2924/00

摘要： A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.

摘要翻译： 一种用于制造互连功能阵列的方法包括在衬底上形成第一多条导线，在第一多条导线和衬底之上形成绝缘体层，去除绝缘体层的部分以限定暴露在绝缘体层中的空腔 衬底和第一多个导电线的部分，其中去除绝缘体层的部分导致暴露衬底和第一多个导电线的部分的空腔的基本上随机的排列，在腔中沉积导电材料 并且在所述空腔和所述绝缘体层中的所述导电材料的部分上形成第二多个导电线。

公开(公告)号：US08716101B2

公开(公告)日：2014-05-06

申请号：US13530999

申请日：2012-06-22

申请人： Kaushik Chandra ,  Ronald G. Filippi ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Chih-Chao Yang

发明人： Kaushik Chandra ,  Ronald G. Filippi ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Chih-Chao Yang

IPC分类号： H01L21/76

CPC分类号： H01L23/528 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer.

摘要翻译： 用于减少半导体器件中的电迁移破裂和挤出效应的结构包括形成在第一介电层中的第一金属线; 形成在第一金属线和第一介电层上的盖层; 形成在所述盖层上的第二电介质层; 以及形成在所述第二介电层中的空隙，停止在所述盖层上，其中所述空隙以这样的方式定位，以便隔离由于所述第一金属线的电迁移效应引起的结构损坏，所述效果包括一种或多种金属挤压 来自第一金属线的材料和帽层相对于第一介电层分层的裂纹。

公开(公告)号：US20130233608A1

公开(公告)日：2013-09-12

申请号：US13414825

申请日：2012-03-08

申请人： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian Yang

发明人： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian Yang

IPC分类号： H05K1/11 ,  B05D5/12 ,  B05D5/00

CPC分类号： H01L23/5222 ,  H01L21/0274 ,  H01L21/3212 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H04L9/3278 ,  H04L2209/12 ,  H05K1/0289 ,  Y10T29/49117 ,  Y10T29/49165 ,  H01L2924/00

摘要： A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.

摘要翻译： 一种用于制造互连功能阵列的方法包括在衬底上形成第一多条导线，在第一多条导线和衬底之上形成绝缘体层，去除绝缘体层的部分以限定暴露在绝缘体层中的空腔 衬底和第一多个导电线的部分，其中去除绝缘体层的部分导致暴露衬底和第一多个导电线的部分的空腔的基本上随机的排列，在腔中沉积导电材料 并且在所述空腔和所述绝缘体层中的所述导电材料的部分上形成第二多个导电线。

公开(公告)号：US20080315353A1

公开(公告)日：2008-12-25

申请号：US11767580

申请日：2007-06-25

申请人： Ping-Chuan Wang ,  Wai-Kin Li

发明人： Ping-Chuan Wang ,  Wai-Kin Li

IPC分类号： H01L23/525 ,  H01L21/71

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to an e-fuse device including an opening, a first via and a second via in an interlayer dielectric, wherein the opening, the first via and the second via are connected to an interconnect below the interlayer dielectric; a dielectric layer that encloses the first via and the second via; and a metal layer over the dielectric layer, wherein the metal layer fills the opening with a metal, and wherein the first via and the second via are substantially empty to allow for electromigration of the interconnect during re-programming of the e-fuse device.

摘要翻译： 本公开总体上涉及集成电路（IC）芯片制造，更具体地，涉及包括开口，层间电介质中的第一通孔和第二通孔的电熔丝装置，其中开口，第一通孔和第二通孔 连接到层间电介质下面的互连; 包围第一通孔和第二通孔的电介质层; 以及在所述介电层上的金属层，其中所述金属层用金属填充所述开口，并且其中所述第一通孔和所述第二通孔基本为空，以允许在所述电熔丝装置的重新编程期间所述互连件的电迁移。