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公开(公告)号：US07422977B2
公开(公告)日：2008-09-09
申请号：US11095567
申请日：2005-04-01
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76834 , H01L21/76846 , H01L21/76849 , H01L21/76864 , H01L21/76867 , Y10S438/927
摘要： A semiconductor device, in which a semiconductor integrated circuit having a multi-level interconnection structure is formed, according to an embodiment of the present invention, comprises a copper wiring and an insulating layer formed on a top surface of the copper wiring, wherein the copper wiring includes an additive for improving adhesion between the copper wiring and the insulating layer, and a profile of the additive has a gradient in which a concentration is gradually reduced as it goes from the top surface of the copper wiring toward the inside thereof, and has the highest concentration on the top surface of the copper wiring.
摘要翻译： 根据本发明实施例的形成有多层互连结构的半导体集成电路的半导体器件包括在铜布线的上表面上形成的铜布线和绝缘层，其中铜 布线包括用于改善铜布线和绝缘层之间的粘附性的添加剂，并且添加剂的轮廓具有随着从铜布线的顶表面朝向其内部逐渐减小浓度的梯度，并且具有 在铜线上表面最高的浓度。
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公开(公告)号：US20060121734A1
公开(公告)日：2006-06-08
申请号：US11095567
申请日：2005-04-01
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76834 , H01L21/76846 , H01L21/76849 , H01L21/76864 , H01L21/76867 , Y10S438/927
摘要： A semiconductor device, in which a semiconductor integrated circuit having a multi-level interconnection structure is formed, according to an embodiment of the present invention, comprises a copper wiring and an insulating layer formed on a top surface of the copper wiring, wherein the copper wiring includes an additive for improving adhesion between the copper wiring and the insulating layer, and a profile of the additive has a gradient in which a concentration is gradually reduced as it goes from the top surface of the copper wiring toward the inside thereof, and has the highest concentration on the top surface of the copper wiring.
摘要翻译： 根据本发明实施例的形成有多层互连结构的半导体集成电路的半导体器件包括在铜布线的上表面上形成的铜布线和绝缘层，其中铜 布线包括用于改善铜布线和绝缘层之间的粘附性的添加剂，并且添加剂的轮廓具有随着从铜布线的顶表面朝向其内部逐渐减小浓度的梯度，并且具有 在铜线上表面最高的浓度。
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3.发明授权Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program product 失效产生图案的方法，制造半导体器件的方法，半导体器件和计算机程序产品公开(公告)号：US07667332B2
公开(公告)日：2010-02-23
申请号：US11265231
申请日：2005-11-03
申请人： Masaaki Hatano , Motoya Okazaki , Junichi Wada , Takeshi Nishioka , Hisashi Kaneko , Takeshi Fujimaki , Kazuyuki Higashi , Kenji Yoshida , Noriaki Matsunaga
发明人： Masaaki Hatano , Motoya Okazaki , Junichi Wada , Takeshi Nishioka , Hisashi Kaneko , Takeshi Fujimaki , Kazuyuki Higashi , Kenji Yoshida , Noriaki Matsunaga
CPC分类号： G06F17/5068
摘要： A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.
摘要翻译： 一种用于产生图案的方法包括：读出互连布局和孔布局;布置规定互连图案的布局布局;布置配置为连接到互连图案的孔图案的孔布局; 在图案处理区域中将在相同互连层级中连接的孔图案中的一个提取到所述互连图案之一; 提取包括所提取的孔图案的第一处理区域; 计算包括在第一处理区域中的互连图案的第一图案密度; 以及基于所述第一图案密度在所述第一处理区域中生成第一附加图案。
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公开(公告)号：US20050093166A1
公开(公告)日：2005-05-05
申请号：US10765833
申请日：2004-01-29
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/532 , H01L23/48 , H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76874 , H01L21/76877 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has an active element structure formed on a semiconductor substrate. A first insulating film is provided above the semiconductor substrate. A first interconnect layer composed of copper is provided in a surface of the first insulating film. A second insulating film is provided on the first insulating film. A connection hole is formed in the second insulating film and has its bottom connected to the first insulating layer. A connection plug composed of a single crystal of copper is filled in the connection hole so that no other crystals of copper are provided in the connection hole. An interconnect trench is formed in a surface of the second insulating film and has its bottom connected to the connection hole. A second interconnect layer is provided in the interconnect trench.
摘要翻译： 半导体器件具有形成在半导体衬底上的有源元件结构。 第一绝缘膜设置在半导体衬底的上方。 由铜构成的第一互连层设置在第一绝缘膜的表面上。 在第一绝缘膜上设置第二绝缘膜。 连接孔形成在第二绝缘膜中，并且其底部连接到第一绝缘层。 在连接孔中填充由铜单晶组成的连接插头，使得连接孔中不设置其他的铜晶体。 互连沟槽形成在第二绝缘膜的表面中，并且其底部连接到连接孔。 第二互连层设置在互连沟槽中。
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公开(公告)号：US06313037B1
公开(公告)日：2001-11-06
申请号：US09576255
申请日：2000-05-24
IPC分类号： H01L2144
CPC分类号： H01L23/485 , H01L21/76807 , H01L21/76885 , H01L23/53214 , H01L23/53238 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor comprising a semiconductor device formed on a semiconductor substrate, an interlevel insulating film having holes and a ring-shaped groove in a circuit area formed on the semiconductor substrate and having the semiconductor element formed therein, the ring-shaped groove seamlessly surrounding an outer periphery of the circuit area, via plugs formed in the holes in the interlevel insulating film, a wiring connected to the plug electrodes and mainly comprising copper, and a via ring having a layer formed in the ring-shaped groove and mainly comprising aluminum, wherein no layer mainly comprising copper is formed in the via ring layer.
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公开(公告)号：US06291891B1
公开(公告)日：2001-09-18
申请号：US09228642
申请日：1999-01-12
申请人： Kazuyuki Higashi , Noriaki Matsunaga , Akihiro Kajita , Tetsuo Matsuda , Tadashi Iijima , Hisashi Kaneko , Hideki Shibata , Naofumi Nakamura , Minakshisundaran Balasubramanian Anand , Tadashi Matsuno , Katsuya Okumura
发明人： Kazuyuki Higashi , Noriaki Matsunaga , Akihiro Kajita , Tetsuo Matsuda , Tadashi Iijima , Hisashi Kaneko , Hideki Shibata , Naofumi Nakamura , Minakshisundaran Balasubramanian Anand , Tadashi Matsuno , Katsuya Okumura
IPC分类号： H01L2348
CPC分类号： H01L21/76852 , H01L21/288 , H01L21/76807 , H01L21/76814 , H01L21/76819 , H01L21/76831 , H01L21/76834 , H01L21/76835 , H01L21/76844 , H01L21/76849 , H01L21/76885 , H01L21/76897 , H01L23/5226 , H01L2221/1026 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.
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7.发明授权Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program 有权用于生成图案的方法，制造半导体器件的方法，半导体器件和计算机程序公开(公告)号：US07996813B2
公开(公告)日：2011-08-09
申请号：US12654865
申请日：2010-01-07
申请人： Masaaki Hatano , Motoya Okazaki , Junichi Wada , Takeshi Nishioka , Hisashi Kaneko , Takeshi Fujimaki , Kazuyuki Higashi , Kenji Yoshida , Noriaki Matsunaga
发明人： Masaaki Hatano , Motoya Okazaki , Junichi Wada , Takeshi Nishioka , Hisashi Kaneko , Takeshi Fujimaki , Kazuyuki Higashi , Kenji Yoshida , Noriaki Matsunaga
IPC分类号： G06F15/04
CPC分类号： G06F17/5068
摘要： A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.
摘要翻译： 一种用于产生图案的方法包括：读出互连布局和孔布局;布置规定互连图案的布局布局;布置配置为连接到互连图案的孔图案的孔布局; 在图案处理区域中将在相同互连层级中连接的孔图案中的一个提取到所述互连图案之一; 提取包括所提取的孔图案的第一处理区域; 计算包括在第一处理区域中的互连图案的第一图案密度; 以及基于所述第一图案密度在所述第一处理区域中生成第一附加图案。
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8.发明申请SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME, AND PATTERN GENERATING METHOD 有权半导体器件，其制造方法和图案生成方法公开(公告)号：US20070158849A1
公开(公告)日：2007-07-12
申请号：US11619338
申请日：2007-01-03
IPC分类号： H01L23/52
CPC分类号： G06F17/5068 , H01L23/564 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to an embodiment of the present invention has: a semiconductor substrate; an interlayer insulating film formed above the semiconductor substrate; a protective film formed on the interlayer insulating film, the protective film having a higher density than that of the interlayer insulating film; at least one of a wiring and a dummy wiring formed in the interlayer insulating film and the protective film; and a separation wall formed within the interlayer insulating film so as to surround a low density region to separate the low density region from other regions, a sum of covering densities of the wiring and the dummy wiring being lower than a predetermined prescribed value in the low density region.
摘要翻译： 根据本发明的实施例的半导体器件具有：半导体衬底; 形成在半导体衬底上的层间绝缘膜; 形成在所述层间绝缘膜上的保护膜，所述保护膜的密度高于所述层间绝缘膜的密度; 在层间绝缘膜和保护膜中形成的布线和虚拟布线中的至少一个; 以及形成在层间绝缘膜内的隔离壁，以便围绕低密度区域以将低密度区域与其他区域分离，布线和虚拟布线的覆盖密度之和低于低于预定的规定值 密度区域。
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公开(公告)号：US07026715B2
公开(公告)日：2006-04-11
申请号：US10628689
申请日：2003-07-28
CPC分类号： H01L21/76802 , H01L21/76801 , H01L21/76804 , H01L21/76807 , H01L21/76829 , H01L23/5222 , H01L23/5226 , H01L23/53228 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is disclosed, which comprises a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, the interlayer insulating film comprising a first insulating film and a second insulating film formed on the first insulating film, the first insulating film comprising a silicon oxide film containing carbon of a concentration, the second insulating film comprising a silicon oxide film containing carbon of a concentration lower than the concentration of the first insulating film or comprising a silicon oxide film containing substantially no carbon, a via contact made of a metal material embedded in a via hole formed in the interlayer insulating film, a diameter of the via hole in the first insulating film being smaller than that in the second insulating film at an interface between the first insulating film and the second insulating film.
摘要翻译： 公开了一种半导体器件，其包括半导体衬底，形成在半导体衬底上的层间绝缘膜，所述层间绝缘膜包括第一绝缘膜和形成在所述第一绝缘膜上的第二绝缘膜，所述第一绝缘膜包括硅 含有浓度为碳的氧化膜，所述第二绝缘膜包含含有浓度低于所述第一绝缘膜的浓度的碳的氧化硅膜，或包含基本上不含碳的氧化硅膜，由金属材料制成的通孔接点 嵌入在所述层间绝缘膜中形成的通路孔中，所述第一绝缘膜中的所述通孔的直径小于所述第一绝缘膜和所述第二绝缘膜之间的界面处的所述第二绝缘膜中的通孔的直径。
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公开(公告)号：US20050285229A1
公开(公告)日：2005-12-29
申请号：US11117726
申请日：2005-04-29
IPC分类号： H01L21/288 , H01L21/46 , H01L21/768 , H01L23/52 , H01L23/532 , H01L23/58
CPC分类号： H01L21/76877 , H01L21/2885 , H01L21/7684 , H01L23/53238 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to an embodiment of the present invention includes a plurality of chip regions and a plurality of chip rings. The plurality of chip regions include semiconductor integrated circuits each having a multilayered wiring structure using a metal wiring, and are formed into independent chips. The plurality of chip rings has the multilayered wiring structure using the metal wiring, and surround the respective chip regions. The plurality of chip rings are electrically connected to one another.
摘要翻译： 根据本发明实施例的半导体器件包括多个芯片区域和多个芯片环。 多个芯片区域包括各自具有使用金属布线的多层布线结构的半导体集成电路，并且形成为独立的芯片。 多个芯片环具有使用金属布线的多层布线结构，并且包围各个芯片区域。 多个芯片环彼此电连接。
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