公开(公告)号：US06291891B1

公开(公告)日：2001-09-18

申请号：US09228642

申请日：1999-01-12

申请人： Kazuyuki Higashi ,  Noriaki Matsunaga ,  Akihiro Kajita ,  Tetsuo Matsuda ,  Tadashi Iijima ,  Hisashi Kaneko ,  Hideki Shibata ,  Naofumi Nakamura ,  Minakshisundaran Balasubramanian Anand ,  Tadashi Matsuno ,  Katsuya Okumura

发明人： Kazuyuki Higashi ,  Noriaki Matsunaga ,  Akihiro Kajita ,  Tetsuo Matsuda ,  Tadashi Iijima ,  Hisashi Kaneko ,  Hideki Shibata ,  Naofumi Nakamura ,  Minakshisundaran Balasubramanian Anand ,  Tadashi Matsuno ,  Katsuya Okumura

IPC分类号： H01L2348

CPC分类号： H01L21/76852 ,  H01L21/288 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2221/1026 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.

公开(公告)号：US5850102A

公开(公告)日：1998-12-15

申请号：US831967

申请日：1997-04-02

申请人： Tadashi Matsuno

发明人： Tadashi Matsuno

IPC分类号： H01L21/285 ,  H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/58

CPC分类号： H01L23/53295 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044

摘要： This invention is related to a metallization of Cu. The semiconductor device comprises a first insulating layer having a groove in a surface thereof, a second insulating layer on a surface of the groove, made of a material having a low density of crystal defects in comparison with that of the first insulating layer, and a wiring layer buried in the groove, surrounded by the second insulating layer.

摘要翻译： 本发明涉及Cu的金属化。 半导体器件包括在其表面上具有凹槽的第一绝缘层，与沟槽的表面上的与第一绝缘层相比具有低密度晶体缺陷的材料制成的第二绝缘层，以及 埋置在槽中的布线层被第二绝缘层包围。

公开(公告)号：US06368951B2

公开(公告)日：2002-04-09

申请号：US09903992

申请日：2001-07-13

申请人： Kazuyuki Higashi ,  Noriaki Matsunaga ,  Akihiro Kajita ,  Tetsuo Matsuda ,  Tadashi Iijima ,  Hisashi Kaneko ,  Hideki Shibata ,  Naofumi Nakamura ,  Minakshisundaran Balasubramanian Anand ,  Tadashi Matsuno ,  Katsuya Okumura

发明人： Kazuyuki Higashi ,  Noriaki Matsunaga ,  Akihiro Kajita ,  Tetsuo Matsuda ,  Tadashi Iijima ,  Hisashi Kaneko ,  Hideki Shibata ,  Naofumi Nakamura ,  Minakshisundaran Balasubramanian Anand ,  Tadashi Matsuno ,  Katsuya Okumura

IPC分类号： H01L214763

CPC分类号： H01L21/76852 ,  H01L21/288 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2221/1026 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.

摘要翻译： 一种半导体器件的制造方法，其特征在于，在形成于半导体衬底上的第一绝缘膜上形成沟槽，在所述沟槽中形成下层配线的工序，在所述半导体衬底上形成至少一层导体层， 在导电层上形成至少一层薄膜层的步骤，通过图案化薄膜形成硬掩模的步骤，通过使用硬掩模作为蚀刻掩模蚀刻导电层的步骤，以及形成 导电柱状结构，其上表面被硬掩模覆盖在下层布线上;在半导体基板上形成第二绝缘膜以使柱状结构被埋设的步骤，形成 至少暴露硬掩模的布线沟槽以及在去除硬掩模之后将导体埋入布线沟槽中的步骤，以及在布线沟槽中形成上层布线。

公开(公告)号：US6051508A

公开(公告)日：2000-04-18

申请号：US145464

申请日：1998-09-02

申请人： Tamao Takase ,  Tadashi Matsuno ,  Hideshi Miyajima

发明人： Tamao Takase ,  Tadashi Matsuno ,  Hideshi Miyajima

IPC分类号： H01L21/768 ,  H01L29/34

CPC分类号： H01L21/7681 ,  H01L21/76802 ,  Y10S438/954

摘要： The present invention intends to form multilayer interconnects without deteriorating the advantage of an organosiloxane film (an interlayer dielectric), i.e., the low dielectric constant. According to the present invention, an organosiloxane film, a silicon nitride film, an inorganic SOG film, and a photoresist pattern are formed on a first metal layer, in series. The inorganic SOG film is then etched with use of the photoresist pattern as a mask to transfer the photoresist pattern to the inorganic SOG film. The photoresist pattern is then removed by oxygen plasma treatment with use of the silicon nitride film as a protection mask for protecting the organosiloxane film. Subsequently thereto, the silicon nitride film and the organosiloxane film are etched with use of the inorganic SOG film to form a contact hole reaching the first metal layer. After removing the inorganic SOG film, a second metal layer is formed to contact with the first metal layer through the contact hole.

摘要翻译： 本发明意图形成多层互连，而不会劣化有机硅氧烷膜（层间电介质）的优点，即低介电常数。 根据本发明，在第一金属层上串联形成有机硅氧烷膜，氮化硅膜，无机SOG膜和光刻胶图案。 然后使用光致抗蚀剂图案作为掩模蚀刻无机SOG膜，以将光致抗蚀剂图案转印到无机SOG膜上。 然后通过使用氮化硅膜作为保护有机硅氧烷膜的保护罩的氧等离子体处理去除光致抗蚀剂图案。 随后，使用无机SOG膜蚀刻氮化硅膜和有机硅氧烷膜，形成到达第一金属层的接触孔。 在去除无机SOG膜之后，形成第二金属层，以通过接触孔与第一金属层接触。

公开(公告)号：US5948698A

公开(公告)日：1999-09-07

申请号：US951164

申请日：1997-10-15

申请人： Masahiro Inohara ,  Tadashi Matsuno

发明人： Masahiro Inohara ,  Tadashi Matsuno

IPC分类号： H01L21/3205 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/762 ,  H01L21/768 ,  H01L21/302

CPC分类号： H01L21/31053 ,  H01L21/3212 ,  H01L21/76229 ,  H01L21/76819 ,  H01L21/7684

摘要： A method for fabricating a semiconductor device at low cost is provided in which a mask layer having a very large polishing selection ratio is used as a polishing stop film by forming the polishing stop film in self-alignment. An object layer to be flattened is formed on a substrate. The object layer contains an irregularity. A polishing stop film which is polished at a slower rate and a mask layer which is polished at about the same rate as the object layer are deposited on the object layer. Then, the mask layer on a high level portion of the object layer is removed by chemical-mechanical polishing. The polishing stop film is etched other than under the mask layer, so that the polishing stop film at the high level portion and side wall of the step is removed. Because the polishing stop film at the convex portions (high level portion) is removed by etching utilizing a chemical reaction without using chemical-mechanical polishing, it is possible to select a material for the polishing stop film which is polished at a very slow rate. After that, the mask layer and the object layer at the convex portion are removed by CMP to level off the object layer with the concave portion.

摘要翻译： 提供了一种以低成本制造半导体器件的方法，其中通过以自对准形成抛光停止膜，将具有非常大的抛光选择比的掩模层用作抛光停止膜。 待平坦化的物体层形成在基板上。 对象层包含不规则。 以较慢的速度抛光的抛光停止膜和以与物体层大致相同的速率抛光的掩模层沉积在物体层上。 然后，通过化学机械抛光去除目标层高层部分上的掩模层。 除了在掩模层下面蚀刻抛光停止膜，从而去除在台阶的高级部分和侧壁处的抛光停止膜。 由于在不使用化学机械抛光的情况下通过化学反应的蚀刻来除去凸部（高级部）的抛光停止膜，因此可以选择以非常慢的速度抛光的抛光停止膜的材料。 之后，通过CMP去除掩模层和凸部处的物体层，使其与凹部平坦化。

公开(公告)号：US5753975A

公开(公告)日：1998-05-19

申请号：US519892

申请日：1995-08-28

申请人： Tadashi Matsuno

发明人： Tadashi Matsuno

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L23/53257 ,  H01L21/76838 ,  H01L23/5329 ,  H01L21/31629 ,  H01L21/76801 ,  H01L2924/0002 ,  Y10S257/915

摘要： A semiconductor device includes a substrate, an insulation film formed above the substrate and containing silicon-fluorine bonds, and a titanium-based metal wiring layer formed on the insulation film, the titanium-based metal wiring layer containing fluorine which is diffused from the insulation film and has a fluorine concentration of less than 1.times.10.sup.20 atoms/cm.sup.3.

公开(公告)号：US6163067A

公开(公告)日：2000-12-19

申请号：US224173

申请日：1998-12-31

申请人： Masahiro Inohara ,  Hideki Shibata ,  Tadashi Matsuno

发明人： Masahiro Inohara ,  Hideki Shibata ,  Tadashi Matsuno

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L23/535

CPC分类号： H01L21/76843 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/7681 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor apparatus and a process for fabricating the same according to the invention permit reduction in width of a wiring pattern of the semiconductor apparatus and in distance between wiring elements. A stopper film and an insulating film are provided on a substrate. The etching rate of RIE for the insulating film is greater than that for the stopper film. The stopper film and insulating film are formed on the insulating film. A pattern of the contact hole is formed in the stopper film. A wiring pattern is formed on the resist film. The insulating films are etched by RIE with the resist film and stopper film used as masks. Thus, a groove for formation of wiring and a contact hole for formation of a contact plug are simultaneously formed in a self-alignment manner.

摘要翻译： 根据本发明的半导体装置及其制造方法允许减小半导体装置的布线图案的宽度和布线元件之间的距离。 在基板上设置有阻挡膜和绝缘膜。 绝缘膜的RIE的蚀刻速率大于阻挡膜的蚀刻速率。 在绝缘膜上形成阻挡膜和绝缘膜。 接触孔的图案形成在止动膜中。 在抗蚀剂膜上形成布线图案。 绝缘膜通过RIE蚀刻，抗蚀剂膜和阻挡膜用作掩模。 因此，用于形成布线的槽和用于形成接触塞的接触孔同时以自对准的方式形成。

公开(公告)号：US5976972A

公开(公告)日：1999-11-02

申请号：US720241

申请日：1996-09-26

申请人： Masahiro Inohara ,  Hideki Shibata ,  Tadashi Matsuno

发明人： Masahiro Inohara ,  Hideki Shibata ,  Tadashi Matsuno

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/768 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/7681 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53223 ,  H01L21/76808 ,  H01L2924/0002

摘要： A semiconductor apparatus and a process for fabricating the same according to the invention permit reduction in width of a wiring pattern of the semiconductor apparatus and in distance between wiring elements. A stopper film and an insulating film are provided on a substrate. The etching rate of RIE for the insulating film is greater than that for the stopper film. The stopper film and insulating film are formed on the insulating film. A pattern of the contact hole is formed in the stopper film. A wiring pattern is formed on the resist film. The insulating films are etched by RIE with the resist film and stopper film used as masks. Thus, a groove for formation of wiring and a contact hole for formation of a contact plug are simultaneously formed in a self-alignment manner.

摘要翻译： 根据本发明的半导体装置及其制造方法允许减小半导体装置的布线图案的宽度和布线元件之间的距离。 在基板上设置有阻挡膜和绝缘膜。 绝缘膜的RIE的蚀刻速率大于阻挡膜的蚀刻速率。 在绝缘膜上形成阻挡膜和绝缘膜。 接触孔的图案形成在止动膜中。 在抗蚀剂膜上形成布线图案。 绝缘膜通过RIE蚀刻，抗蚀剂膜和阻挡膜用作掩模。 因此，用于形成布线的槽和用于形成接触塞的接触孔同时以自对准的方式形成。

公开(公告)号：US6004887A

公开(公告)日：1999-12-21

申请号：US969649

申请日：1997-11-13

申请人： Tadashi Matsuno

发明人： Tadashi Matsuno

IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L23/532 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L23/5329 ,  H01L21/76838 ,  H01L23/53257 ,  H01L21/31629 ,  H01L21/76801 ,  H01L2924/0002

摘要： A semiconductor device includes a substrate, an insulation film formed above the substrate and containing silicon-fluorine bonds, and a titanium-based metal wiring layer formed on the insulation film, the titanium-based metal wiring layer containing fluorine which is diffused from the insulation film and has a fluorine concentration of less than 1.times.10.sup.20 atoms/cm.sup.3.

公开(公告)号：US5874779A

公开(公告)日：1999-02-23

申请号：US969647

申请日：1997-11-13

申请人： Tadashi Matsuno

发明人： Tadashi Matsuno

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L23/53257 ,  H01L21/76838 ,  H01L23/5329 ,  H01L21/31629 ,  H01L21/76801 ,  H01L2924/0002 ,  Y10S257/915

摘要： A semiconductor device includes a substrate, an insulation film formed above the substrate and containing silicon-fluorine bonds, and a titanium-based metal wiring layer formed on the insulation film, the titanium-based metal wiring layer containing fluorine which is diffused from the insulation film and has a fluorine concentration of less than 1.times.10.sup.20 atoms/cm.sup.3.

摘要翻译： 半导体器件包括基板，形成在基板上并含有硅 - 氟键的绝缘膜和形成在绝缘膜上的钛基金属布线层，含有从绝缘体扩散的氟的钛基金属布线层 并且具有小于1×10 20原子/ cm 3的氟浓度。