公开(公告)号：US5528054A

公开(公告)日：1996-06-18

申请号：US416110

申请日：1995-04-03

申请人： Takashi Ipposhi ,  Kazuyuki Sugahara

发明人： Takashi Ipposhi ,  Kazuyuki Sugahara

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L29/78 ,  H01L29/04

CPC分类号： H01L29/66772 ,  H01L21/2026 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/0688 ,  H01L21/76272 ,  H01L21/76281 ,  H01L27/1203

摘要： Generation of new crystal defects in a monocrystalline semiconductor layer caused by heat treatment, oxidation treatment or polishing treatment is prevented in a method of manufacturing a semiconductor device of an SOI structure. Thus, unevenness in the properties of active devices formed on the monocrystalline semiconductor layers and their malfunctions can be restrained. A non-monocrystalline semiconductor layer formed on an insulator layer is melted to have a prescribed temperature distribution, and monocrystallized. The region of the obtained monocrystalline semiconductor layer corresponding to a high temperature portion in melting is selectively removed before the monocrystalline semiconductor layer is subjected to heat-treatment. Active devices are formed on the resultant island shaped monocrystalline semiconductor layers. The surface of the island shaped monocrystalline semiconductor layer may be polished to be planarized before the formation of the active device.

摘要翻译： 在SOI结构的半导体器件的制造方法中，防止了由热处理，氧化处理或抛光处理引起的单晶半导体层中的新的晶体缺陷的产生。 因此，可以抑制在单晶半导体层上形成的有源器件的特性及其故障的不均匀性。 形成在绝缘体层上的非单晶半导体层被熔化成具有规定的温度分布，并进行单晶化。 在对单晶半导体层进行热处理之前，选择性地去除与熔融温度高的部分相对应的所获得的单晶半导体层的区域。 在所形成的岛状单晶半导体层上形成有源器件。 在形成有源器件之前，岛状单晶半导体层的表面可以被抛光以被平坦化。

公开(公告)号：US5355022A

公开(公告)日：1994-10-11

申请号：US936390

申请日：1992-08-28

申请人： Kazuyuki Sugahara ,  Natsuo Ajika ,  Toshiaki Ogawa ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Kazuyuki Sugahara ,  Natsuo Ajika ,  Toshiaki Ogawa ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L27/00 ,  H01L21/02 ,  H01L21/20 ,  H01L21/762 ,  H01L21/822 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L27/02 ,  H01L23/48

CPC分类号： H01L21/2007 ,  H01L21/76251 ,  H01L21/8221 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896

摘要： In a method of manufacturing a stacked-type semiconductor device, firstly, a first semiconductor substrate having a first device formed thereon is covered with an interlayer insulating layer and a planarized polycrystalline silicon layer is formed on the interlayer insulating layer. The first semiconductor substrate and a second semiconductor substrate are joined together by putting the surface of the polycrystalline silicon layer in close contact with the surface of a refractory metal layer formed on the second semiconductor substrate, applying thermal treatment at 700.degree. C. or below and changing the refractory metal layer to silicide.

摘要翻译： 在叠层型半导体器件的制造方法中，首先，在层间绝缘层上形成有具有形成在其上的第一器件的第一半导体衬底，层间绝缘层形成平坦化的多晶硅层。 将第一半导体衬底和第二半导体衬底通过将多晶硅层的表面与形成在第二半导体衬底上的难熔金属层的表面紧密接触，在700℃以下进行热处理， 将难熔金属层改为硅化物。

公开(公告)号：US5214001A

公开(公告)日：1993-05-25

申请号：US640499

申请日：1991-01-14

申请人： Takashi Ipposhi ,  Kazuyuki Sugahara

发明人： Takashi Ipposhi ,  Kazuyuki Sugahara

IPC分类号： H01L21/20 ,  H01L21/304 ,  H01L21/762

CPC分类号： H01L21/304 ,  H01L21/2026 ,  H01L21/76248

摘要： A manufacturing method of a semiconductor device having a planar single crystal semiconductor surface is disclosed. In the manufacturing method of a semiconductor device, an insulating film is formed on a semiconductor substrate, a noncrystal semiconductor film is formed on the insulating film, a stripe-like anti-reflection film is formed on the noncrystal semiconductor film, and laser beam is irradiated along the anti-reflection film. Because of the difference in temperature, a film with thicknesses different in a substrate region in which the anti-reflection film is formed and a region around it is formed. A film to be a machining allowance for polishing is formed on the single crystal semiconductor film, polishing is performed from the side of said film to be a machining allowance for polishing so that desired planar film thickness of the single crystal semiconductor film is implemented.

摘要翻译： 公开了具有平面单晶半导体表面的半导体器件的制造方法。 在半导体装置的制造方法中，在半导体基板上形成绝缘膜，在绝缘膜上形成非晶半导体膜，在非晶半导体膜上形成条状的防反射膜，激光束为 沿抗反射膜照射。 由于温度的差异，形成了在其中形成防反射膜的基板区域和其周围的区域具有不同厚度的膜。 在单晶半导体膜上形成作为研磨加工余量的膜，从所述膜的侧面进行研磨，作为研磨用的加工余量，从而实现单晶半导体膜的期望的平面膜厚。

公开(公告)号：US5514880A

公开(公告)日：1996-05-07

申请号：US142564

申请日：1993-10-28

申请人： Hisayuki Nishimura ,  Kazuyuki Sugahara ,  Shigenobu Maeda ,  Takashi Ipposhi ,  Yasuo Inoue ,  Toshiaki Iwamatsu ,  Mikio Ikeda ,  Tatsuya Kunikiyo ,  Junji Tateishi ,  Tadaharu Minato

发明人： Hisayuki Nishimura ,  Kazuyuki Sugahara ,  Shigenobu Maeda ,  Takashi Ipposhi ,  Yasuo Inoue ,  Toshiaki Iwamatsu ,  Mikio Ikeda ,  Tatsuya Kunikiyo ,  Junji Tateishi ,  Tadaharu Minato

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786 ,  H01L29/10 ,  H01L29/06

CPC分类号： H01L27/11 ,  H01L27/1108 ,  H01L29/78654 ,  H01L27/1281 ,  Y10S257/903

摘要： In a miniaturized complete CMOS SRAM of a TFT load type, a field effect thin-film transistor (TFT) can achieve stable reading and writing operation of a memory cell and can reduce power consumption thereof. The field effect thin-film transistor formed on an insulator includes an active layer and a gate electrode. The gate electrode is formed on a channel region of the active layer with a gate insulating film therebetween. The active layer is formed of a channel region and source/drain regions. The channel region is formed of a monocrystal silicon layer and does not includes a grain boundary. The source/drain regions is formed of a polysilicon layer. The channel region has a density of crystal defects of less than 10.sup.9 pieces/cm.sup.2. The thin film transistor shows an ON current of 0.25 .mu.A/.mu.m per channel width of 1 .mu.m and an OFF current of 15 fA/.mu.m. The thin-film transistor can be applied to a p-channel MOS transistor serving as a load transistor in a memory cell of a CMOS type SRAM.

摘要翻译： 在TFT负载型的小型化的完全CMOS SRAM中，场效应薄膜晶体管（TFT）能够实现对存储单元的稳定的读/写操作并且可以降低其功耗。 形成在绝缘体上的场效应薄膜晶体管包括有源层和栅电极。 栅电极形成在有源层的沟道区上，其间具有栅极绝缘膜。 有源层由沟道区和源极/漏极区形成。 沟道区由单晶硅层形成，不包含晶界。 源/漏区由多晶硅层形成。 沟道区域的晶体缺陷密度小于109个/ cm 2。 薄膜晶体管的通道宽度为1μm，导通电流为0.25μA/μm，OFF电流为15fA /μm。 薄膜晶体管可以被施加到用作CMOS型SRAM的存储单元中的负载晶体管的p沟道MOS晶体管。

公开(公告)号：US5504376A

公开(公告)日：1996-04-02

申请号：US222502

申请日：1994-04-04

申请人： Kazuyuki Sugahara ,  Natsuo Ajika ,  Toshiaki Ogawa ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Kazuyuki Sugahara ,  Natsuo Ajika ,  Toshiaki Ogawa ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L27/00 ,  H01L21/02 ,  H01L21/20 ,  H01L21/762 ,  H01L21/822 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L27/02 ,  H01L23/48

CPC分类号： H01L21/2007 ,  H01L21/76251 ,  H01L21/8221 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896

摘要： In a method of manufacturing a stacked-type semiconductor device, firstly, a first semiconductor substrate having a first device formed thereon is covered with an interlayer insulating layer and a planarized polycrystalline silicon layer is formed on the interlayer insulating layer. The first semiconductor substrate and a second semiconductor substrate are joined together by putting the surface of the polycrystalline silicon layer in close contact with the surface of a refractory metal layer formed on the second semiconductor substrate, applying thermal treatment at 700.degree. C. or below and changing the refractory metal layer to silicide.

摘要翻译： 在叠层型半导体器件的制造方法中，首先，在层间绝缘层上形成有具有形成在其上的第一器件的第一半导体衬底，层间绝缘层形成平坦化的多晶硅层。 将第一半导体衬底和第二半导体衬底通过将多晶硅层的表面与形成在第二半导体衬底上的难熔金属层的表面紧密接触，在700℃以下进行热处理， 将难熔金属层改为硅化物。

公开(公告)号：US5413968A

公开(公告)日：1995-05-09

申请号：US22876

申请日：1993-02-25

申请人： Yasuo Inoue ,  Kazuyuki Sugahara ,  Takashi Ipposhi ,  Yasuo Yamaguchi ,  Tadashi Nishimura

发明人： Yasuo Inoue ,  Kazuyuki Sugahara ,  Takashi Ipposhi ,  Yasuo Yamaguchi ,  Tadashi Nishimura

IPC分类号： H01L21/3205 ,  H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L23/52 ,  H01L23/522 ,  H01L27/11 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L23/485 ,  H01L27/11 ,  H01L27/1112 ,  H01L2924/0002

摘要： A semiconductor device includes a conductor layer (3, 7) having a silicon crystal, an insulator layer (5, 15) formed on the surface of the conductor layer (3, 7) having a contact hole therethrough to said surface of the conductor layer (3, 7), an interconnecting portion formed at a predetermined location in the insulator layer (5, 15) and having a contact hole (6, 9) the bottom surface of which becomes the surface of the conductor layer (3, 7), a barrier layer (14) formed at the bottom of said contact hole at least on the surface of the conductor layer (3, 7) in the interconnecting portion, and a metal silicide layer (12) formed on the barrier layer (14). This semiconductor device is manufactured by depositing the insulator layer (5, 15) having the contact hole (6, 9) on the conductor layer (3, 7) having the silicon crystal, forming the barrier layer (14) and the polysilicon layer (7, 10) overlapping each other in the contact hole (6, 9) and on the insulator layer (5, 15) and then patterning these overlapping barrier layer (14) and polysilicon layer (7, 10), forming a metal layer (8, 11) thereon to be silicidized, and removing unreacted metal. The semiconductor device thus manufactured prevents a suction of silicon from the conductor layer (3, 7) to the metal silicide layer (12) and hence prevents an increase in resistance value due to a deficiency of silicon produced in the conductor layer (3, 7), thereby minimizing a series resistance of the metal silicide layer (12), a contact portion and the conductor layer (3, 7).

摘要翻译： 半导体器件包括具有硅晶体的导体层（3,7），形成在导体层（3,7）的表面上的绝缘体层（5,15），其具有穿过其的导体层的所述表面的接触孔 （3,7），形成在所述绝缘体层（5,15）中的预定位置处并具有其底表面成为所述导体层（3,7）的表面的接触孔（6,9）的互连部分， 至少在所述互连部分中的所述导体层（3,7）的表面上形成在所述接触孔的底部处的阻挡层（14）和形成在所述阻挡层（14）上的金属硅化物层（12） 。 该半导体器件通过在具有硅晶体的导体层（3,7）上沉积具有接触孔（6,9）的绝缘体层（5,15），形成阻挡层（14）和多晶硅层（ 7,10）在接触孔（6,9）和绝缘体层（5,15）上彼此重叠，然后对这些重叠的阻挡层（14）和多晶硅层（7,10）进行构图，形成金属层 8,11）在其上被硅化，并除去未反应的金属。 这样制造的半导体器件防止硅从导体层（3,7）吸收到金属硅化物层（12），从而防止由于导体层（3,7）中产生的硅的缺陷导致的电阻值增加 ），从而使金属硅化物层（12），接触部分和导体层（3,7）的串联电阻最小化。

公开(公告)号：US5006913A

公开(公告)日：1991-04-09

申请号：US430402

申请日：1989-11-02

申请人： Kazuyuki Sugahara ,  Shigeru Kusunoki ,  Takashi Ipposhi

发明人： Kazuyuki Sugahara ,  Shigeru Kusunoki ,  Takashi Ipposhi

IPC分类号： H01L21/822 ,  H01L27/06

CPC分类号： H01L21/8221 ,  H01L27/0688

摘要： A field effect transistor is formed as a first semiconductor element on a main surface of a first semiconductor layer (1). An interlayer insulating film (10) constituted by a first insulating layer (101) and a second insulating layer (102) is formed on the first semiconductor element. The first insulating layer (101) is formed of a BPSG film having a glass transition point no higher than 750.degree. C. The second insulating layer (102) is formed of a silicon oxide film having a glass transition point higher than 750.degree. C. and a thickness no less than 2000 .ANG. and no more than 1 .mu.m formed on the first insulating layer (101). A second semiconductor layer (11) is formed on the second insulating layer (102) of the interlayer insulating film (10). The second semiconductor layer (11) is formed to be an island, with the peripheral portions isolated. A field effect transistor as a second semiconductor element is formed in the second semiconductor layer (11). The first insulating layer (101) suppresses stress remained in the second semiconductor layer (11) derived from a difference between coefficient of thermal expansion of the second semiconductor layer (11) and the interlayer insulating film (10). The second insulating layer (102) suppresses lateral distortion generated in the semiconductor layer (11). The characteristics of the second semiconductor element can be improved.

摘要翻译： 在第一半导体层（1）的主表面上形成场效应晶体管作为第一半导体元件。 在第一半导体元件上形成由第一绝缘层（101）和第二绝缘层（102）构成的层间绝缘膜（10）。 第一绝缘层（101）由玻璃化转变点不高于750℃的BPSG膜形成。第二绝缘层（102）由玻璃化转变点高于750℃的氧化硅膜形成。 并且在第一绝缘层（101）上形成的厚度不小于2000，不大于1μm。 在层间绝缘膜（10）的第二绝缘层（102）上形成第二半导体层（11）。 第二半导体层（11）形成为岛状，其外围部分被隔离。 在第二半导体层（11）中形成作为第二半导体元件的场效应晶体管。 第一绝缘层（101）抑制由第二半导体层（11）和层间绝缘膜（10）之间的热膨胀系数之差导出的第二半导体层（11）中残留的应力。 第二绝缘层（102）抑制在半导体层（11）中产生的横向失真。 可以提高第二半导体元件的特性。

公开(公告)号：US5736438A

公开(公告)日：1998-04-07

申请号：US483411

申请日：1995-06-07

申请人： Hisayuki Nishimura ,  Kazuyuki Sugahara ,  Shigenobu Maeda ,  Takashi Ipposhi ,  Yasuo Inoue ,  Toshiaki Iwamatsu ,  Mikio Ikeda ,  Tatsuya Kunikiyo ,  Junji Tateishi ,  Tadaharu Minato

发明人： Hisayuki Nishimura ,  Kazuyuki Sugahara ,  Shigenobu Maeda ,  Takashi Ipposhi ,  Yasuo Inoue ,  Toshiaki Iwamatsu ,  Mikio Ikeda ,  Tatsuya Kunikiyo ,  Junji Tateishi ,  Tadaharu Minato

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786 ,  H01L21/84

CPC分类号： H01L27/11 ,  H01L27/1108 ,  H01L29/78654 ,  H01L27/1281 ,  Y10S257/903

摘要： In a miniaturized complete CMOS SRAM of a TFT load type, a field effect thin-film transistor (TFT) can achieve stable reading and writing operation of a memory cell and can reduce power consumption thereof. The field effect thin-film transistor formed on an insulator includes an active layer and a gate electrode. The gate electrode is formed on a channel region of the active layer with a gate insulating film therebetween. The active layer is formed of a channel region and source/drain regions. The channel region is formed of a monocrystal silicon layer and does not includes a grain boundary. The source/drain regions is formed of a polysilicon layer. The channel region has a density of crystal defects of less than 10.sup.9 pieces/cm.sup.2. The thin film transistor shows an ON current of 0.25 .mu.A/.mu.m per channel width of 1 .mu.m and an OFF current of 15 fA/.mu.m. The thin-film transistor can be applied to a p-channel MOS transistor serving as a load transistor in a memory cell of a CMOS type SRAM.

摘要翻译： 在TFT负载型的小型化的完全CMOS SRAM中，场效应薄膜晶体管（TFT）能够实现对存储单元的稳定的读/写操作并且可以降低其功耗。 形成在绝缘体上的场效应薄膜晶体管包括有源层和栅电极。 栅电极形成在有源层的沟道区上，其间具有栅极绝缘膜。 有源层由沟道区和源极/漏极区形成。 沟道区由单晶硅层形成，不包含晶界。 源/漏区由多晶硅层形成。 沟道区域的晶体缺陷密度小于109个/ cm 2。 薄膜晶体管的通道宽度为1μm，导通电流为0.25μA/μm，OFF电流为15fA /μm。 薄膜晶体管可以被施加到用作CMOS型SRAM的存储单元中的负载晶体管的p沟道MOS晶体管。

公开(公告)号：US5338388A

公开(公告)日：1994-08-16

申请号：US877811

申请日：1992-05-04

申请人： Kazuyuki Sugahara ,  Takashi Ipposhi

发明人： Kazuyuki Sugahara ,  Takashi Ipposhi

IPC分类号： H01L21/20 ,  H01L21/762 ,  H01L21/822 ,  C30B23/02

CPC分类号： H01L21/2026 ,  H01L21/8221 ,  H01L21/76272 ,  H01L21/76281 ,  Y10S117/904

摘要： A method of forming single-crystal semiconductor films, in which a single-crystal semiconductor substrate having a crystal axis transferred from a single-crystal semiconductor substrate is formed on an insulator layer via a seed hole which goes through the insulator layer which is formed on the single-crystal semiconductor substrate, comprises the steps of: forming a non-single-crystal semiconductor substrate connected to a single-crystal semiconductor substrate via a seed hole on an insulator layer; irradiating a compound beam which includes a first energy beam having a power density which is capable of melting a non-single-crystal semiconductor film and a second energy beam having a power density which is not capable of melting the non-single-crystal semiconductor film but capable of softening the insulator layer positioned below the non-single-crystal semiconductor film; and epitaxially growing the single-crystal semiconductor film in such a way that the non-single-crystal semiconductor film is melted and then solidified again by scanning the surface of the non-single-crystal semiconductor film with the compound beam, starting from the seed hole, in such a manner that the first energy beam is irradiated first and the second energy beam is irradiated second.

摘要翻译： 一种形成单晶半导体膜的方法，其中具有从单晶半导体衬底转移的晶轴的单晶半导体衬底经由穿过形成于绝缘体层上的绝缘体层的籽晶孔形成在绝缘体层上 单晶半导体衬底包括以下步骤：通过绝缘体层上的晶种孔形成与单晶半导体衬底连接的非单晶半导体衬底; 照射包括具有能够熔化非单晶半导体膜的功率密度的第一能量束和不能熔化非单晶半导体膜的功率密度的第二能量束的复合光束 但能够使位于非单晶半导体膜下方的绝缘体层软化; 并以这样的方式外延生长单晶半导体膜，使得非晶单晶半导体膜通过从种子开始通过用复合束扫描非单晶半导体膜的表面再次熔化然后再固化 孔，首先照射第一能量束，并且第二能量束被照射。

公开(公告)号：US20070105329A1

公开(公告)日：2007-05-10

申请号：US11617936

申请日：2006-12-29

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L29/76 ,  H01L21/8222

CPC分类号： H01L27/0617 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/13 ,  H01L28/10 ,  H01L28/20 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： Plural trench isolation films are provided with portions of an SOI layer interposed therebetween in a surface of the SOI layer in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive element are formed on the trench isolation films, respectively. Each of the trench isolation films includes a central portion which passes through the SOI layer and reaches a buried oxide film to include a full-trench isolation structure, and opposite side portions each of which passes through only a portion of the SOI layer and is located on the SOI layer to include a partial-trench isolation structure. Thus, each of the trench isolation films includes a hybrid-trench isolation structure.

摘要翻译： 多个沟槽隔离膜在其中设置有螺旋电感器（SI）的电阻器区域（RR）中的SOI层的表面中设置有SOI层的部分。 电阻元件分别形成在沟槽隔离膜上。 每个沟槽隔离膜包括穿过SOI层并到达掩埋氧化膜以包括全沟槽隔离结构的中心部分，以及相对的侧部，其每个仅穿过SOI层的一部分并且位于 在SOI层上以包括部分沟槽隔离结构。 因此，每个沟槽隔离膜包括混合沟槽隔离结构。