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    Methods of operating an electronic circuit for measurement of transistor variability and the like
    1.
    发明授权
    Methods of operating an electronic circuit for measurement of transistor variability and the like 失效
    操作用于测量晶体管可变性等的电子电路的方法

    公开(公告)号：US07764080B2

    公开(公告)日：2010-07-27

    申请号：US12200334

    申请日：2008-08-28

    申请人： Keith A. Jenkins ,  Jae-Joon Kim ,  Rahul M. Rao

    发明人： Keith A. Jenkins ,  Jae-Joon Kim ,  Rahul M. Rao

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2621

    摘要： An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided. The gate of the first measuring field effect transistor is energized; the gates of the field effect transistors to be tested are sequentially energized, whereby an output voltage appears on the output terminal; and the output voltage is compared to the reference value.

    摘要翻译： 电子电路包括输出端子和至少第一测量FET。 待测试的多个FET的第二漏极 - 源极端子与第一测量FET和输出端子的第一漏极 - 源极端子互连。 第一测量FET的第二漏极 - 源极端子与第一偏置端子互连。 要测试的FETS的第一漏极 - 源极端子与第二偏置端子互连。 状态机耦合到要测试的FETs的栅极和第一测量FET的栅极。 状态机被配置为对第一测量FET的栅极通电并且顺序地激励要测试的FETS的栅极，使得输出电压出现在输出端子上。 还提供了将输出电压与参考值进行比较的电路。 第一测量场效应晶体管的栅极通电; 要测试的场效应晶体管的栅极依次通电，从而输出电压出现在输出端上; 并将输出电压与参考值进行比较。

    ELECTRONIC CIRCUIT FOR MEASUREMENT OF TRANSISTOR VARIABILITY AND THE LIKE
    2.
    发明申请
    ELECTRONIC CIRCUIT FOR MEASUREMENT OF TRANSISTOR VARIABILITY AND THE LIKE 有权
    用于测量晶体管可变性和类似物的电子电路

    公开(公告)号：US20090309625A1

    公开(公告)日：2009-12-17

    申请号：US12542184

    申请日：2009-08-17

    申请人： Keith A. Jenkins ,  Jae-Joon Kim ,  Rahul M. Rao

    发明人： Keith A. Jenkins ,  Jae-Joon Kim ,  Rahul M. Rao

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2621

    摘要： An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided. The gate of the first measuring field effect transistor is energized; the gates of the field effect transistors to be tested are sequentially energized, whereby an output voltage appears on the output terminal; and the output voltage is compared to the reference value.

    摘要翻译： 电子电路包括输出端子和至少第一测量FET。 待测试的多个FET的第二漏极 - 源极端子与第一测量FET和输出端子的第一漏极 - 源极端子互连。 第一测量FET的第二漏极 - 源极端子与第一偏置端子互连。 要测试的FETS的第一漏极 - 源极端子与第二偏置端子互连。 状态机耦合到要测试的FETs的栅极和第一测量FET的栅极。 状态机被配置为对第一测量FET的栅极通电并且顺序地激励要测试的FETS的栅极，使得输出电压出现在输出端子上。 还提供了将输出电压与参考值进行比较的电路。 第一测量场效应晶体管的栅极通电; 要测试的场效应晶体管的栅极依次通电，从而输出电压出现在输出端上; 并将输出电压与参考值进行比较。

    Electronic circuit for measurement of transistor variability and the like
    3.
    发明授权
    Electronic circuit for measurement of transistor variability and the like 有权
    用于测量晶体管变化性的电子电路等

    公开(公告)号：US08004305B2

    公开(公告)日：2011-08-23

    申请号：US12542184

    申请日：2009-08-17

    申请人： Keith A. Jenkins ,  Jae-Joon Kim ,  Rahul M. Rao

    发明人： Keith A. Jenkins ,  Jae-Joon Kim ,  Rahul M. Rao

    IPC分类号： G01R31/02

    CPC分类号： G01R31/2621

    摘要： An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided. The gate of the first measuring field effect transistor is energized; the gates of the field effect transistors to be tested are sequentially energized, whereby an output voltage appears on the output terminal; and the output voltage is compared to the reference value.

    摘要翻译： 电子电路包括输出端子和至少第一测量FET。 待测试的多个FET的第二漏极 - 源极端子与第一测量FET和输出端子的第一漏极 - 源极端子互连。 第一测量FET的第二漏极 - 源极端子与第一偏置端子互连。 要测试的FETS的第一漏极 - 源极端子与第二偏置端子互连。 状态机耦合到要测试的FETs的栅极和第一测量FET的栅极。 状态机被配置为对第一测量FET的栅极通电并且顺序地激励要测试的FETS的栅极，使得输出电压出现在输出端子上。 还提供了将输出电压与参考值进行比较的电路。 第一测量场效应晶体管的栅极通电; 要测试的场效应晶体管的栅极依次通电，从而输出电压出现在输出端上; 并将输出电压与参考值进行比较。

    Electronic circuit for measurement of transistor variability and the like
    4.
    发明授权
    Electronic circuit for measurement of transistor variability and the like 有权
    用于测量晶体管变化性的电子电路等

    公开(公告)号：US07439755B2

    公开(公告)日：2008-10-21

    申请号：US11669250

    申请日：2007-01-31

    申请人： Keith A. Jenkins ,  Jae-Joon Kim ,  Rahul M. Rao

    发明人： Keith A. Jenkins ,  Jae-Joon Kim ,  Rahul M. Rao

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2621

    摘要： An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided.

    摘要翻译： 电子电路包括输出端子和至少第一测量FET。 待测试的多个FET的第二漏极 - 源极端子与第一测量FET和输出端子的第一漏极 - 源极端子互连。 第一测量FET的第二漏极 - 源极端子与第一偏置端子互连。 要测试的FETS的第一漏极 - 源极端子与第二偏置端子互连。 状态机耦合到要测试的FETs的栅极和第一测量FET的栅极。 状态机被配置为对第一测量FET的栅极通电并且顺序地激励要测试的FETS的栅极，使得输出电压出现在输出端子上。 还提供了将输出电压与参考值进行比较的电路。

    On-Chip Delay Measurement Through a Transistor Array
    5.
    发明申请
    On-Chip Delay Measurement Through a Transistor Array 审中-公开
    通过晶体管阵列进行片上延迟测量

    公开(公告)号：US20130049791A1

    公开(公告)日：2013-02-28

    申请号：US13601122

    申请日：2012-08-31

    申请人： Keith A. Jenkins ,  Jae-Joon Kim ,  Rahul M. Rao

    发明人： Keith A. Jenkins ,  Jae-Joon Kim ,  Rahul M. Rao

    IPC分类号： G01R31/26

    CPC分类号： G11C29/023 ,  G01R31/31725 ,  G11C2029/5002

    摘要： A delay is measured through an array of transistors by selecting one transistor in the array; and applying a clock signal to the selected transistor. An output of the selected transistor is applied to a first input of a logic gate and a second clock signal based on the clock signal is applied to a second input of the logic gate. An output of the logic gate indicates a difference in arrival times of the signals at the two inputs. A clock signal can be applied to the selected transistor and a variable delay circuit. An output of the selected transistor is applied to a data input of a latch while an output of the variable delay circuit is applied to a clock input of the latch. The delay applied by the variable delay circuit is adjusted until a predefined transition is detected. The delay variation among the transistors can be obtained.

    摘要翻译： 通过选择阵列中的一个晶体管，通过晶体管阵列来测量延迟; 以及将时钟信号施加到所选择的晶体管。 所选择的晶体管的输出被施加到逻辑门的第一输入，并且基于时钟信号的第二时钟信号被施加到逻辑门的第二输入。 逻辑门的输出表示两个输入端的信号的到达时间差。 时钟信号可以施加到所选择的晶体管和可变延迟电路。 所选择的晶体管的输出被施加到锁存器的数据输入，而可变延迟电路的输出被施加到锁存器的时钟输入。 调整由可变延迟电路施加的延迟，直到检测到预定的转换。 可以获得晶体管之间的延迟变化。

    On-Chip Delay Measurement Through a Transistor Array
    6.
    发明申请
    On-Chip Delay Measurement Through a Transistor Array 审中-公开
    通过晶体管阵列进行片上延迟测量

    公开(公告)号：US20120081141A1

    公开(公告)日：2012-04-05

    申请号：US12894334

    申请日：2010-09-30

    申请人： Keith A. Jenkins ,  Jae-Joon Kim ,  Rahul M. Rao

    发明人： Keith A. Jenkins ,  Jae-Joon Kim ,  Rahul M. Rao

    IPC分类号： G01R31/26

    CPC分类号： G11C29/023 ,  G01R31/31725 ,  G11C2029/5002

    摘要： Methods and apparatus are provided for measuring a delay through one or more transistors in an array of transistors. The delay through one or more transistors in an array of transistors is measured by selecting one of the transistors in the array; and applying a clock signal to the selected transistor, wherein an output of the selected transistor is applied to a first input of a logic gate having at least two inputs and wherein a second clock signal based on the clock signal is applied to a second input of the logic gate, and wherein an output of the logic gate indicates a difference in arrival times of the signals at the two inputs. In one variation, a clock signal is applied to the selected transistor and a variable delay circuit; and an output of the selected transistor is applied to a data input of a latch having a clock input and a data input while an output of the variable delay circuit is applied to a clock input of the latch. The delay applied by the variable delay circuit to the clock signal is adjusted until a predefined transition is detected in an output of the latch. If the delay is measured through a plurality of transistors in the array, the delay variation among the plurality of transistors can be obtained.

    摘要翻译： 提供了用于测量晶体管阵列中的一个或多个晶体管的延迟的方法和装置。 通过选择阵列中的一个晶体管来测量晶体管阵列中的一个或多个晶体管的延迟; 以及将时钟信号施加到所选择的晶体管，其中所选择的晶体管的输出被施加到具有至少两个输入的逻辑门的第一输入，并且其中基于时钟信号的第二时钟信号被施加到 逻辑门，并且其中逻辑门的输出指示两个输入处的信号的到达时间的差异。 在一个变型中，时钟信号被施加到所选择的晶体管和可变延迟电路; 并且所选择的晶体管的输出被施加到具有时钟输入和数据输入的锁存器的数据输入端，而可变延迟电路的输出被施加到锁存器的时钟输入端。 调整由可变延迟电路施加到时钟信号的延迟，直到在锁存器的输出中检测到预定的转换。 如果通过阵列中的多个晶体管测量延迟，则可以获得多个晶体管之间的延迟变化。

    Methods of Operating an Electronic Circuit for Measurement of Transistor Variability and the Like
    7.
    发明申请
    Methods of Operating an Electronic Circuit for Measurement of Transistor Variability and the Like 失效
    操作电子电路测量晶体管变异性等的方法

    公开(公告)号：US20080315907A1

    公开(公告)日：2008-12-25

    申请号：US12200334

    申请日：2008-08-28

    申请人： Keith A. Jenkins ,  Jae-Joon Kim ,  Rahul M. Rao

    发明人： Keith A. Jenkins ,  Jae-Joon Kim ,  Rahul M. Rao

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2621

    摘要： An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided. The gate of the first measuring field effect transistor is energized; the gates of the field effect transistors to be tested are sequentially energized, whereby an output voltage appears on the output terminal; and the output voltage is compared to the reference value.

    摘要翻译： 电子电路包括输出端子和至少第一测量FET。 待测试的多个FET的第二漏极 - 源极端子与第一测量FET和输出端子的第一漏极 - 源极端子互连。 第一测量FET的第二漏极 - 源极端子与第一偏置端子互连。 要测试的FETS的第一漏极 - 源极端子与第二偏置端子互连。 状态机耦合到要测试的FETs的栅极和第一测量FET的栅极。 状态机被配置为对第一测量FET的栅极通电并且顺序地激励要测试的FETS的栅极，使得输出电压出现在输出端子上。 还提供了将输出电压与参考值进行比较的电路。 第一测量场效应晶体管的栅极通电; 要测试的场效应晶体管的栅极依次通电，从而输出电压出现在输出端上; 并将输出电压与参考值进行比较。

    Electronic Circuit for Measurement of Transistor Variability and the Like
    8.
    发明申请
    Electronic Circuit for Measurement of Transistor Variability and the Like 有权
    晶体管可变性测量用电子电路等

    公开(公告)号：US20080180134A1

    公开(公告)日：2008-07-31

    申请号：US11669250

    申请日：2007-01-31

    申请人： Keith A. Jenkins ,  Jae-Joon Kim ,  Rahul M. Rao

    发明人： Keith A. Jenkins ,  Jae-Joon Kim ,  Rahul M. Rao

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2621

    摘要： An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided.

    摘要翻译： 电子电路包括输出端子和至少第一测量FET。 待测试的多个FET的第二漏极 - 源极端子与第一测量FET和输出端子的第一漏极 - 源极端子互连。 第一测量FET的第二漏极 - 源极端子与第一偏置端子互连。 要测试的FETS的第一漏极 - 源极端子与第二偏置端子互连。 状态机耦合到要测试的FETs的栅极和第一测量FET的栅极。 状态机被配置为对第一测量FET的栅极通电并且顺序地激励要测试的FETS的栅极，使得输出电压出现在输出端子上。 还提供了将输出电压与参考值进行比较的电路。