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    Method for fabricating thin-film transistor
    1.
    发明授权
    Method for fabricating thin-film transistor 失效
    制造薄膜晶体管的方法

    公开(公告)号：US06338990B1

    公开(公告)日：2002-01-15

    申请号：US09177050

    申请日：1998-10-23

    申请人： Ken-ichi Yanai ,  Tsutomu Tanaka ,  Koji Ohgata ,  Yutaka Takizawa ,  Ken-ichi Oki ,  Takuya Hirano

    发明人： Ken-ichi Yanai ,  Tsutomu Tanaka ,  Koji Ohgata ,  Yutaka Takizawa ,  Ken-ichi Oki ,  Takuya Hirano

    IPC分类号： H01L2100

    CPC分类号： H01L29/78696 ,  G02F1/1368 ,  H01L21/0242 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/28525 ,  H01L29/458 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78603 ,  H01L29/78618

    摘要： To form a contact layer on source and drain electrodes of a stagger-type TFT, a conductive material is selectively sticked to the surface of the source and drain electrodes and a contact layer is selectively deposited by using the conductive material as growth species to form an active semiconductor layer on the contact layer. For an inverted-stagger-type TFT, a conductive material is selectively deposited on the surface of a contact layer to use the selectively deposited conductive material as source and drain electrodes so that patterning is unnecessary. To selectively deposit a contact layer of a TFT by alternately repeating etching and deposition, the temperature for the etching is set to 200° C. or lower. A contaminated layer on the surface of a semiconductor film serving as an active semiconductor layer and contact layer of a TFT is removed by plasma at the temperature of 200° C. or lower. For a stagger-type thin-film transistor, the hydrogen or halogen content of an insulating film serving as the substrate of source and drain electrodes is increased. For an inverted-stagger thin-film transistor, the hydrogen or halogen content of an insulating film serving as a channel protective film is increased. Thus, the etching rate of the surfaces of these insulating films by plasma increases.

    摘要翻译： 为了在交错型TFT的源极和漏极上形成接触层，导电材料选择性地粘附到源电极和漏电极的表面，并且通过使用导电材料作为生长物质选择性地沉积接触层，以形成 接触层上的有源半导体层。 对于反交错型TFT，在接触层的表面上选择性地沉积导电材料，以使用选择性沉积的导电材料作为源极和漏极，使得不需要图案化。 为了通过交替重复蚀刻和沉积来选择性地沉积TFT的接触层，蚀刻温度设定为200℃以下。 用作有源半导体层的半导体膜的表面上的污染层和TFT的接触层通过等离子体在200℃以下的温度下除去。 对于错开型薄膜晶体管，增加了用作源极和漏极电极的衬底的绝缘膜的氢或卤素含量。 对于倒置的薄膜晶体管，作为沟道保护膜的绝缘膜的氢或卤素含量增加。 因此，通过等离子体的这些绝缘膜的表面的蚀刻速率增加。

    Method for fabricating a thin-film transistor
    2.
    发明授权
    Method for fabricating a thin-film transistor 失效
    薄膜晶体管的制造方法

    公开(公告)号：US5470768A

    公开(公告)日：1995-11-28

    申请号：US102248

    申请日：1993-08-05

    申请人： Ken-ichi Yanai ,  Tsutomu Tanaka ,  Koji Ohgata ,  Yutaka Takizawa ,  Ken-ichi Oki ,  Takuya Hirano

    发明人： Ken-ichi Yanai ,  Tsutomu Tanaka ,  Koji Ohgata ,  Yutaka Takizawa ,  Ken-ichi Oki ,  Takuya Hirano

    IPC分类号： G02F1/1368 ,  H01L21/205 ,  H01L21/285 ,  H01L21/336 ,  H01L29/45 ,  H01L29/786 ,  H01L21/86

    CPC分类号： H01L29/78696 ,  H01L21/0242 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/28525 ,  H01L29/458 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78603 ,  H01L29/78618 ,  G02F1/1368

    摘要： To form a contact layer on source and drain electrodes of a stagger-type TFT, a conductive material is selectively sticked to the surface of the source and drain electrodes and a contact layer is selectively deposited by using the conductive material as growth species to form an active semiconductor layer on the contact layer. For an inverted-stagger-type TFT, a conductive material is selectively deposited on the surface of a contact layer to use the selectively deposited conductive material as source and drain electrodes so that patterning is unnecessary. To selectively deposit a contact layer of a TFT by alternately repeating etching and deposition, the temperature for the etching is set to 200.degree. C. or lower. A contaminated layer on the surface of a semiconductor film serving as an active semiconductor layer and contact layer of a TFT is removed by plasma at the temperature of 200.degree. C. or lower. For a stagger-type thin-film transistor, the hydrogen or halogen content of an insulating film serving as the substrate of source and drain electrodes is increased. For an inverted-stagger thin-film transistor, the hydrogen or halogen content of an insulating film serving as a channel protective film is increased. Thus, the etching rate of the surfaces of these insulating films by plasma increases.

    摘要翻译： 为了在交错型TFT的源极和漏极上形成接触层，导电材料选择性地粘附到源电极和漏电极的表面，并且通过使用导电材料作为生长物质选择性地沉积接触层，以形成 接触层上的有源半导体层。 对于反交错型TFT，在接触层的表面上选择性地沉积导电材料，以使用选择性沉积的导电材料作为源极和漏极，使得不需要图案化。 为了通过交替重复蚀刻和沉积来选择性地沉积TFT的接触层，蚀刻温度设定为200℃以下。 用作有源半导体层的半导体膜的表面上的污染层和TFT的接触层通过等离子体在200℃或更低的温度下去除。 对于错开型薄膜晶体管，增加了用作源极和漏极电极的衬底的绝缘膜的氢或卤素含量。 对于倒置的薄膜晶体管，作为沟道保护膜的绝缘膜的氢或卤素含量增加。 因此，通过等离子体的这些绝缘膜的表面的蚀刻速率增加。

    Method for fabricating thin-film transistor
    3.
    发明授权
    Method for fabricating thin-film transistor 失效
    制造薄膜晶体管的方法

    公开(公告)号：US5879973A

    公开(公告)日：1999-03-09

    申请号：US510563

    申请日：1995-08-02

    申请人： Ken-ichi Yanai ,  Tsutomu Tanaka ,  Koji Ohgata ,  Yutaka Takizawa ,  Ken-ichi Oki ,  Takuya Hirano

    发明人： Ken-ichi Yanai ,  Tsutomu Tanaka ,  Koji Ohgata ,  Yutaka Takizawa ,  Ken-ichi Oki ,  Takuya Hirano

    IPC分类号： G02F1/1368 ,  H01L21/205 ,  H01L21/285 ,  H01L21/336 ,  H01L29/45 ,  H01L29/786 ,  H01L21/84

    CPC分类号： H01L29/78696 ,  H01L21/0242 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/28525 ,  H01L29/458 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78603 ,  H01L29/78618 ,  G02F1/1368

    摘要： To form a contact layer on source and drain electrodes of a stagger-type TFT, a conductive material is selectively sticked to the surface of the source and drain electrodes and a contact layer is selectively deposited by using the conductive material as growth species to form an active semiconductor layer on the contact layer. For an inverted-stagger-type TFT, a conductive material is selectively deposited on the surface of a contact layer to use the selectively deposited conductive material as source and drain electrodes so that patterning is unnecessary. To selectively deposit a contact layer of a TFT by alternately repeating etching and deposition, the temperature for the etching is set to 200.degree. C. or lower. A contaminated layer on the surface of a semiconductor film serving as an active semiconductor layer and contact layer of a TFT is removed by plasma at the temperature of 200.degree. C. or lower. For a stagger-type thin-film transistor, the hydrogen or halogen content of an insulating film serving as the substrate of source and drain electrodes is increased. For an inverted-stagger thin-film transistor, the hydrogen or halogen content of an insulating film serving as a channel protective film is increased. Thus, the etching rate of the surfaces of these insulating films by plasma increases.

    摘要翻译： 为了在交错型TFT的源极和漏极上形成接触层，导电材料选择性地粘附到源电极和漏电极的表面，并且通过使用导电材料作为生长物质选择性地沉积接触层，以形成 接触层上的有源半导体层。 对于反交错型TFT，在接触层的表面上选择性地沉积导电材料，以使用选择性沉积的导电材料作为源极和漏极，使得不需要图案化。 为了通过交替重复蚀刻和沉积来选择性地沉积TFT的接触层，蚀刻温度设定为200℃以下。 用作有源半导体层的半导体膜的表面上的污染层和TFT的接触层通过等离子体在200℃或更低的温度下去除。 对于错开型薄膜晶体管，增加了用作源极和漏极电极的衬底的绝缘膜的氢或卤素含量。 对于倒置的薄膜晶体管，作为沟道保护膜的绝缘膜的氢或卤素含量增加。 因此，通过等离子体的这些绝缘膜的表面的蚀刻速率增加。

    Thin film transistor matrix device
    4.
    发明授权
    Thin film transistor matrix device 失效
    薄膜晶体管矩阵器件

    公开(公告)号：US6130456A

    公开(公告)日：2000-10-10

    申请号：US956772

    申请日：1997-10-22

    申请人： Ken-ichi Oki ,  Ken-ichi Yanai ,  Tamotsu Wada ,  Koji Ohgata ,  Yutaka Takizawa ,  Masahiro Okabe ,  Tsutomu Tanaka

    发明人： Ken-ichi Oki ,  Ken-ichi Yanai ,  Tamotsu Wada ,  Koji Ohgata ,  Yutaka Takizawa ,  Masahiro Okabe ,  Tsutomu Tanaka

    IPC分类号： G02F1/1362 ,  G02F1/1368 ,  H01L21/77 ,  H01L21/84

    CPC分类号： H01L27/124 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136295 ,  H01L29/41733

    摘要： A thin film transistor matrix device comprises an insulating substrate, a plurality of picture element electrodes arranged in a matrix on the insulating substrate, source electrodes connected to the respective picture element electrodes, drain electrodes opposed to the respective source electrodes, operational semiconductor layers sandwiched by the source electrodes and the drain electrodes, and gate electrodes formed on the operational semiconductor layers through gate insulating films, each gate electrode being narrowed with respect to the associated gate insulating film so that side walls of the gate electrode forms a step with respect to side walls of the associated gate insulating film which is a substrate of the gate electrode. The gate electrode is made narrower with respect to the gate insulating film to form a step between the side walls of the gate electrode with respect to those of the gate insulating film, whereby leak currents from the source electrode or the drain electrode to the gate electrode along the mesa side surfaces of the TFT can be simply suppressed. Accordingly a TFT matrix device having little wasteful current consumption can be realized.

    摘要翻译： 薄膜晶体管矩阵器件包括绝缘衬底，在绝缘衬底上以矩阵形式布置的多个像素电极，连接到各个像素电极的源电极，与各个源电极相对的漏极电极，被 源电极和漏极以及通过栅极绝缘膜形成在工作半导体层上的栅电极，每个栅电极相对于相关的栅极绝缘膜变窄，使得栅电极的侧壁相对于侧面形成一个台阶 作为栅电极的基板的相关栅极绝缘膜的壁。 使栅电极相对于栅极绝缘膜变窄，在栅电极的侧壁之间相对于栅极绝缘膜的侧壁形成台阶，由此从源电极或漏电极到栅电极的漏电流 沿着TFT的台面侧表面可以简单地抑制。 因此，可以实现具有少量浪费电流消耗的TFT矩阵装置。

    Thin film transistor matrix device and method for fabricating the same
    5.
    发明授权
    Thin film transistor matrix device and method for fabricating the same 失效
    制造薄膜晶体管矩阵器件的方法

    公开(公告)号：US5994173A

    公开(公告)日：1999-11-30

    申请号：US941224

    申请日：1997-09-26

    申请人： Ken-ichi Oki ,  Ken-ichi Yanai ,  Tamotsu Wada ,  Koji Ohgata ,  Yutaka Takizawa ,  Masahiro Okabe ,  Tsutomu Tanaka

    发明人： Ken-ichi Oki ,  Ken-ichi Yanai ,  Tamotsu Wada ,  Koji Ohgata ,  Yutaka Takizawa ,  Masahiro Okabe ,  Tsutomu Tanaka

    IPC分类号： G02F1/1362 ,  G02F1/1368 ,  H01L21/77 ,  H01L21/84 ,  H01L31/0392 ,  H01L21/306 ,  H01L29/78

    CPC分类号： H01L27/124 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136295 ,  H01L29/41733

    摘要： A thin film transistor matrix device comprises an insulating substrate, a plurality of picture element electrodes arranged in a matrix on the insulating substrate, source electrodes connected to the respective picture element electrodes, drain electrodes opposed to the respective source electrodes, operational semiconductor layers sandwiched by the source electrodes and the drain electrodes, and gate electrodes formed on the operational semiconductor layers through gate insulating films, each gate electrode being narrowed with respect to the associated gate insulating film so that side walls of the gate electrode forms a step with respect to side walls of the associated gate insulating film which is a substrate of the gate electrode. The gate electrode is made narrower with respect to the gate insulating film to form a step between the side walls of the gate electrode with respect to those of the gate insulating film, whereby leak currents from the source electrode or the drain electrode to the gate electrode along the mesa side surfaces of the TFT can be simply suppressed. Accordingly a TFT matrix device having little wasteful current consumption can be realized.

    摘要翻译： 薄膜晶体管矩阵器件包括绝缘衬底，在绝缘衬底上以矩阵形式布置的多个像素电极，连接到各个像素电极的源电极，与各个源电极相对的漏极电极，被 源电极和漏极以及通过栅极绝缘膜形成在工作半导体层上的栅电极，每个栅电极相对于相关的栅极绝缘膜变窄，使得栅电极的侧壁相对于侧面形成一个台阶 作为栅电极的基板的相关栅极绝缘膜的壁。 使栅电极相对于栅极绝缘膜变窄，在栅电极的侧壁之间相对于栅极绝缘膜的侧壁形成台阶，由此从源电极或漏电极到栅电极的漏电流 沿着TFT的台面侧表面可以简单地抑制。 因此，可以实现具有少量浪费电流消耗的TFT矩阵装置。

    Method for fabricating a thin film transistor matrix device
    6.
    发明授权
    Method for fabricating a thin film transistor matrix device 失效
    制造薄膜晶体管矩阵器件的方法

    公开(公告)号：US5728592A

    公开(公告)日：1998-03-17

    申请号：US499000

    申请日：1995-07-06

    申请人： Ken-ichi Oki ,  Ken-ichi Yanai ,  Tamotsu Wada ,  Koji Ohgata ,  Yutaka Takizawa ,  Masahiro Okabe ,  Tsutomu Tanaka

    发明人： Ken-ichi Oki ,  Ken-ichi Yanai ,  Tamotsu Wada ,  Koji Ohgata ,  Yutaka Takizawa ,  Masahiro Okabe ,  Tsutomu Tanaka

    IPC分类号： G02F1/1362 ,  G02F1/1368 ,  H01L21/77 ,  H01L21/84 ,  H01L21/288 ,  H01L21/31

    CPC分类号： H01L27/124 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136295 ,  H01L29/41733

    摘要： A thin film transistor matrix device is fabricated by forming a transparent conductor film and a metal film on an insulating substrate in this order. The metal film and the transparent conductor film are together patterned to form picture element electrodes, and drain bus lines or gate bus lines. Source electrodes and drain electrodes may also be formed from the transparent conductor film and metal film. A semiconductor layer, an insulating film and a conductor film may be formed on the entire surface in this order. In this case, the conductor film, the insulator film and the semiconductor layer are patterned to form an active layer from the semiconductor layer, gate insulating films from the insulating film, and gate electrodes and gate bus lines from the conductor film. By patterning the conductor film, the insulating film and the semiconductor layer, the metal film of the picture element electrodes and drain bus lines is exposed. Alternatively, the metal film may be patterned with the semiconductor layer, insulating film and conductor film to expose the transparent conductor film. A current is applied to the drain bus lines or gate bus lines in an electrolyte solution to selectively form a film on the drain bus lines or gate bus lines. The film may be a protecting film serving as a mask to allow the metal film on the picture element electrodes to be etched.

    摘要翻译： 通过在绝缘基板上依次形成透明导体膜和金属膜来制造薄膜晶体管矩阵器件。 金属膜和透明导体膜一起构图以形成像素电极，以及漏极总线或栅极总线。 源电极和漏电极也可以由透明导体膜和金属膜形成。 可以依次在整个表面上形成半导体层，绝缘膜和导体膜。 在这种情况下，对导体膜，绝缘体膜和半导体层进行构图，从半导体层形成有源层，从绝缘膜形成栅极绝缘膜，从导体膜形成栅极电极和栅极总线。 通过图案化导体膜，绝缘膜和半导体层，使像素电极和漏极总线的金属膜露出。 或者，可以用半导体层，绝缘膜和导体膜对金属膜进行图案化以使透明导体膜露出。 在电解质溶液中的漏极总线或栅极总线上施加电流以在漏极总线或栅极总线上选择性地形成膜。 该膜可以是用作掩模的保护膜，以允许蚀刻图像元件电极上的金属膜。

    CMOS-type semiconductor device and method of fabricating the same
    10.
    发明授权
    CMOS-type semiconductor device and method of fabricating the same 有权
    CMOS型半导体器件及其制造方法

    公开(公告)号：US06635521B2

    公开(公告)日：2003-10-21

    申请号：US09277880

    申请日：1999-03-29

    申请人： Hongyong Zhang ,  Makoto Igarashi ,  Kenichi Yanai ,  Tetsuro Hori ,  Yutaka Takizawa

    发明人： Hongyong Zhang ,  Makoto Igarashi ,  Kenichi Yanai ,  Tetsuro Hori ,  Yutaka Takizawa

    IPC分类号： H01L218238

    CPC分类号： H01L27/127 ,  H01L27/1214 ,  H01L27/1274

    摘要： In the fabrication of a CMOS-TFT, non-selectively doping (for both of p- and n-type TFTS) and selectively doping (only for the n-type TFT) with p-type impurities (B: boron) are successively performed at very low concentrations to control the threshold voltages (Vthp and Vthn). More specifically, the Id-Vg characteristics of the p- and n-type TFTs are initially negatively shifted. In this state, non-selectively doping is performed positively to shift the p- and n-type TFTs first to adjust the Vthp to a specified value. Selectively doping is then performed positively to shift only the n-type TFT to adjust the Vthn to a specified value. The threshold voltages of the p- and n-type TFTs constructing the CMOS-TFT can be independently and efficiently (with minimum photolithography) controlled with high accuracy.

    摘要翻译： 在CMOS-TFT的制造中，对p型杂质（B：硼）进行非选择性掺杂（对于p型和n型TFTS两者）和选择性掺杂（仅对于n型TFT），依次进行 以非常低的浓度控制阈值电压（Vthp和Vthn）。 更具体地说，p型和n型TFT的Id-Vg特性最初是负偏移的。 在这种状态下，非选择性地掺杂是首先进行p型和n型TFT移位，以将Vthp调节到规定值。 然后选择性地掺杂以仅仅移动n型TFT以将Vthn调节到指定值。 构成CMOS-TFT的p型和n型TFT的阈值电压可以以高精度独立而有效地（最小光刻）进行控制。