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    Method of manufacturing CMOS semiconductor device
    1.
    发明授权
    Method of manufacturing CMOS semiconductor device 有权
    制造CMOS半导体器件的方法

    公开(公告)号：US06881653B2

    公开(公告)日：2005-04-19

    申请号：US10740430

    申请日：2003-12-22

    申请人： Manabu Kojima ,  Kenichi Goto ,  Hiroshi Morioka ,  Kenichi Okabe

    发明人： Manabu Kojima ,  Kenichi Goto ,  Hiroshi Morioka ,  Kenichi Okabe

    IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L21/20

    CPC分类号： H01L21/823842

    摘要： A method of manufacturing a CMOS semiconductor device able to reduce the effective thickness of the gate insulating film and able to secure stable performance is provided. The method in one embodiment comprises the steps of: forming a polycrystalline silicon film on a gate insulating film; introducing an n-type impurity into the polycrystalline silicon film in an nMOS formation region before gate processing of the polycrystalline silicon film; performing heat treatment so that the impurity diffuses in the polycrystalline silicon film and is activated; and patterning the polycrystalline silicon to form a gate pattern before introducing an impurity into the polycrystalline silicon film at a pMOS formation region.

    摘要翻译： 提供了能够降低栅极绝缘膜的有效厚度并能够确保稳定性能的CMOS半导体器件的制造方法。 一个实施例中的方法包括以下步骤：在栅极绝缘膜上形成多晶硅膜; 在多晶硅膜的栅极处理之前，在nMOS形成区域中将n型杂质引入到多晶硅膜中; 进行热处理，使得杂质在多晶硅膜中扩散并被活化; 以及在pMOS形成区域向多晶硅膜中引入杂质之前，形成多晶硅以形成栅极图案。

    Manufacture of semiconductor device with selective amorphousizing
    2.
    发明申请
    Manufacture of semiconductor device with selective amorphousizing 审中-公开
    具有选择性非晶化的半导体器件的制造

    公开(公告)号：US20050236667A1

    公开(公告)日：2005-10-27

    申请号：US11169666

    申请日：2005-06-30

    申请人： Kenichi Goto ,  Hiroshi Morioka ,  Manabu Kojima ,  Kenichi Okabe

    发明人： Kenichi Goto ,  Hiroshi Morioka ,  Manabu Kojima ,  Kenichi Okabe

    IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/45

    CPC分类号： H01L21/26506 ,  H01L21/28035 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/6659 ,  H01L29/7833

    摘要： A p-channel MOS transistor capable of lowering the height of a gate electrode, suppressing penetration of boron through a gate insulating film, and reducing a source/drain parasitic capacitance. A method for manufacturing a semiconductor device comprises the steps of: (a) forming a gate insulating film on each surface of active regions including an n-type active region; (b) depositing a poly-Si gate electrode layer on the gate insulating film; (c) implanting amorphousizing ions, Ge or Si, to transform an upper portion of the gate electrode layer into amorphous phase; (d) patterning the gate electrode layer to form a gate electrode; (e) forming side wall spacers on side walls of the gate electrode at a temperature not crystallizing the amorphous layer; and (f) implanting p-type impurity ions, B, into the n-type active region by using as a mask the gate electrode and the side wall spacers, to form high concentration source/drain regions.

    摘要翻译： 能够降低栅电极的高度的p沟道MOS晶体管，抑制硼穿过栅极绝缘膜的渗透，并降低源/漏寄生电容。 一种制造半导体器件的方法包括以下步骤：（a）在包括n型有源区的有源区的每个表面上形成栅极绝缘膜; （b）在栅极绝缘膜上沉积多晶硅栅电极层; （c）注入非晶化离子Ge或Si，以将栅电极层的上部转变成非晶相; （d）图案化栅电极层以形成栅电极; （e）在不使非晶层结晶的温度下，在栅电极的侧壁上形成侧壁间隔物; 和（f）通过使用栅电极和侧壁间隔物作为掩模将p型杂质离子B注入到n型有源区中，以形成高浓度源/漏区。

    Method of manufacturing semiconductor device
    3.
    发明授权
    Method of manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07883960B2

    公开(公告)日：2011-02-08

    申请号：US12409979

    申请日：2009-03-24

    申请人： Masatoshi Fukuda ,  Akiyoshi Hatada ,  Katsuaki Ookoshi ,  Kenichi Okabe ,  Tomonari Yamamoto

    发明人： Masatoshi Fukuda ,  Akiyoshi Hatada ,  Katsuaki Ookoshi ,  Kenichi Okabe ,  Tomonari Yamamoto

    IPC分类号： H01L21/8234 ,  H01L21/8244 ,  H01L21/8242 ,  H01L21/336

    CPC分类号： H01L27/0629

    摘要： A method of manufacturing a semiconductor device includes forming a conductive layer over a semiconductor substrate, selectively removing the conductive layer for forming a resistance element and a gate electrode, forming sidewall spacers over sidewalls of the remaining conductive layer, forming a first insulating film containing a nitrogen over the semiconductor substrate having the sidewall spacers, implanting ions in the semiconductor substrate through the first insulating film, forming a second insulating film containing a nitrogen over the first insulating film after implanting ions in the semiconductor substrate through the first insulating film, and selectively removing the first and the second insulating film such that at least a part of the first and the second insulating films is remained over the semiconductor substrate and over the conductive layer.

    摘要翻译： 一种制造半导体器件的方法包括在半导体衬底上形成导电层，选择性地去除用于形成电阻元件和栅电极的导电层，在剩余导电层的侧壁上形成侧壁间隔物，形成第一绝缘膜， 在具有侧壁间隔物的半导体衬底上的氮气，通过第一绝缘膜在半导体衬底中注入离子，在通过第一绝缘膜植入离子到半导体衬底中之后，在第一绝缘膜上形成含有氮的第二绝缘膜，并且选择性地 去除第一和第二绝缘膜，使得第一和第二绝缘膜的至少一部分保留在半导体衬底上并在导电层上方。

    Semiconductor device and manufacturing method thereof
    7.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US07838401B2

    公开(公告)日：2010-11-23

    申请号：US12550727

    申请日：2009-08-31

    申请人： Hiroyuki Ohta ,  Kenichi Okabe

    发明人： Hiroyuki Ohta ,  Kenichi Okabe

    IPC分类号： H01L21/265

    CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    摘要： A semiconductor device comprises a field-effect transistor arranged in a semiconductor substrate, which transistor has a gate electrode, source/drain impurity diffusion regions, and carbon layers surrounding the source/drain impurity diffusion regions. Each of the carbon layers is provided at an associated of the source/drain impurity diffusion regions and positioned so as to be offset from the front edge of a source/drain extension in direction away from the gate electrode and to surround as profile the associated source/drain impurity diffusion region.

    摘要翻译： 半导体器件包括布置在半导体衬底中的场效应晶体管，该晶体管具有栅电极，源/漏杂质扩散区和围绕源极/漏极杂质扩散区的碳层。 每个碳层设置在源极/漏极杂质扩散区域的相关联处，并且被定位成从远离栅电极的方向偏离源极/漏极延伸部的前边缘，并且作为轮廓围绕相关源 /漏杂质扩散区域。