公开(公告)号：US07883960B2

公开(公告)日：2011-02-08

申请号：US12409979

申请日：2009-03-24

申请人： Masatoshi Fukuda ,  Akiyoshi Hatada ,  Katsuaki Ookoshi ,  Kenichi Okabe ,  Tomonari Yamamoto

发明人： Masatoshi Fukuda ,  Akiyoshi Hatada ,  Katsuaki Ookoshi ,  Kenichi Okabe ,  Tomonari Yamamoto

IPC分类号： H01L21/8234 ,  H01L21/8244 ,  H01L21/8242 ,  H01L21/336

CPC分类号： H01L27/0629

摘要： A method of manufacturing a semiconductor device includes forming a conductive layer over a semiconductor substrate, selectively removing the conductive layer for forming a resistance element and a gate electrode, forming sidewall spacers over sidewalls of the remaining conductive layer, forming a first insulating film containing a nitrogen over the semiconductor substrate having the sidewall spacers, implanting ions in the semiconductor substrate through the first insulating film, forming a second insulating film containing a nitrogen over the first insulating film after implanting ions in the semiconductor substrate through the first insulating film, and selectively removing the first and the second insulating film such that at least a part of the first and the second insulating films is remained over the semiconductor substrate and over the conductive layer.

摘要翻译： 一种制造半导体器件的方法包括在半导体衬底上形成导电层，选择性地去除用于形成电阻元件和栅电极的导电层，在剩余导电层的侧壁上形成侧壁间隔物，形成第一绝缘膜， 在具有侧壁间隔物的半导体衬底上的氮气，通过第一绝缘膜在半导体衬底中注入离子，在通过第一绝缘膜植入离子到半导体衬底中之后，在第一绝缘膜上形成含有氮的第二绝缘膜，并且选择性地 去除第一和第二绝缘膜，使得第一和第二绝缘膜的至少一部分保留在半导体衬底上并在导电层上方。

公开(公告)号：US08575704B2

公开(公告)日：2013-11-05

申请号：US13415482

申请日：2012-03-08

申请人： Masaki Haneda ,  Akiyoshi Hatada ,  Akira Katakami ,  Yuka Kase ,  Kazuya Okubo

发明人： Masaki Haneda ,  Akiyoshi Hatada ,  Akira Katakami ,  Yuka Kase ,  Kazuya Okubo

IPC分类号： H01L21/70 ,  H01L21/336

CPC分类号： H01L21/823481 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/28202 ,  H01L21/76229 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： A semiconductor device includes a semiconductor substrate, a device region including first and second parts, first and second gate electrodes formed in the first and the second parts, first and second source regions, first and second drain regions, first, second, third, and fourth embedded isolation film regions formed under the first source, the first drain, the second source, and the second drain regions, respectively. Further, the first drain region and the second source region form a single diffusion region, the second and the third embedded isolation film regions form a single embedded isolation film region, an opening is formed in a part of the single diffusion region so as to extend to the second and the third embedded isolation film regions, and the opening is filled with an isolation film.

摘要翻译： 半导体器件包括半导体衬底，包括第一和第二部分的器件区域，形成在第一和第二部分中的第一和第二栅电极，第一和第二源极区域，第一和第二漏极区域，第一，第二，第三和第 分别形成在第一源极，第一漏极，第二源极和第二漏极区域之下的第四嵌入式隔离膜区域。 此外，第一漏极区域和第二源极区域形成单个扩散区域，第二和第三嵌入式隔离膜区域形成单个嵌入式隔离膜区域，在单个扩散区域的一部分中形成开口以延伸 到第二和第三嵌入式隔离膜区域，并且开口填充有隔离膜。

公开(公告)号：US20120261760A1

公开(公告)日：2012-10-18

申请号：US13415482

申请日：2012-03-08

申请人： Masaki Haneda ,  Akiyoshi Hatada ,  Akira Katakami ,  Yuka Kase ,  Kazuya Okubo

发明人： Masaki Haneda ,  Akiyoshi Hatada ,  Akira Katakami ,  Yuka Kase ,  Kazuya Okubo

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L21/823481 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/28202 ,  H01L21/76229 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： A semiconductor device includes a semiconductor substrate, a device region including first and second parts, first and second gate electrodes formed in the first and the second parts, first and second source regions, first and second drain regions, first, second, third, and fourth embedded isolation film regions formed under the first source, the first drain, the second source, and the second drain regions, respectively. Further, the first drain region and the second source region form a single diffusion region, the second and the third embedded isolation film regions form a single embedded isolation film region, an opening is formed in a part of the single diffusion region so as to extend to the second and the third embedded isolation film regions, and the opening is filled with an isolation film.

摘要翻译： 半导体器件包括半导体衬底，包括第一和第二部分的器件区域，形成在第一和第二部分中的第一和第二栅电极，第一和第二源极区域，第一和第二漏极区域，第一，第二，第三和第 分别形成在第一源极，第一漏极，第二源极和第二漏极区域之下的第四嵌入式隔离膜区域。 此外，第一漏极区域和第二源极区域形成单个扩散区域，第二和第三嵌入式隔离膜区域形成单个嵌入式隔离膜区域，在单个扩散区域的一部分中形成开口以延伸 到第二和第三嵌入式隔离膜区域，并且开口填充有隔离膜。

公开(公告)号：US08278177B2

公开(公告)日：2012-10-02

申请号：US13240303

申请日：2011-09-22

申请人： Yosuke Shimamune ,  Masahiro Fukuda ,  Young Suk Kim ,  Akira Katakami ,  Akiyoshi Hatada ,  Naoyoshi Tamura ,  Hiroyuki Ohta

发明人： Yosuke Shimamune ,  Masahiro Fukuda ,  Young Suk Kim ,  Akira Katakami ,  Akiyoshi Hatada ,  Naoyoshi Tamura ,  Hiroyuki Ohta

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.

摘要翻译： 在沟槽中通过外延生长法形成第一p型SiGe混晶层，形成第二p型SiGe混晶层。 在第二SiGe混晶层上形成第三p型SiGe混晶层。 从沟槽底部开始的第一SiGe混合晶体层的最上表面的高度低于沟槽的深度，硅衬底的表面是标准的。 从沟槽底部开始的第二SiGe混合晶体层的最上表面的高度高于沟槽的深度，硅衬底的表面是标准的。 第一和第三SiGe混晶层中的Ge浓度低于第二SiGe混晶层中的Ge浓度。

公开(公告)号：US6159858A

公开(公告)日：2000-12-12

申请号：US884165

申请日：1997-06-27

申请人： Sadahiro Kishii ,  Ko Nakamura ,  Yoshihiro Arimoto ,  Akiyoshi Hatada ,  Rintaro Suzuki ,  Naruo Ueda ,  Kenzo Hanawa

发明人： Sadahiro Kishii ,  Ko Nakamura ,  Yoshihiro Arimoto ,  Akiyoshi Hatada ,  Rintaro Suzuki ,  Naruo Ueda ,  Kenzo Hanawa

IPC分类号： C03C19/00 ,  C09G1/02 ,  C09K3/14 ,  C09K13/04 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/302

CPC分类号： C09G1/02 ,  C03C19/00 ,  C09K3/1409 ,  C09K3/1463 ,  C09K3/1472 ,  C09K13/04 ,  H01L21/02065 ,  H01L21/02074 ,  H01L21/31053 ,  H01L21/3212

摘要： A slurry contains MnO.sub.2 or other manganese oxide as a primary component of abrasive particles. Further, a polishing process using such a manganese oxide abrasive and a fabrication process of a semiconductor device using such a polishing process are disclosed.

摘要翻译： 浆料含有MnO 2或其它氧化锰作为磨料颗粒的主要成分。 此外，公开了使用这种氧化锰研磨剂的研磨工艺和使用这种抛光工艺的半导体器件的制造工艺。

公开(公告)号：US5877089A

公开(公告)日：1999-03-02

申请号：US14246

申请日：1998-01-27

申请人： Sadahiro Kishii ,  Akiyoshi Hatada ,  Rintaro Suzuki ,  Hiroshi Horie ,  Yoshihiro Arimoto ,  Ko Nakamura

发明人： Sadahiro Kishii ,  Akiyoshi Hatada ,  Rintaro Suzuki ,  Hiroshi Horie ,  Yoshihiro Arimoto ,  Ko Nakamura

IPC分类号： C09G1/02 ,  C09K3/14 ,  H01L21/3105 ,  H01L21/463

CPC分类号： H01L21/31053 ,  C09G1/02 ,  C09K3/1463 ,  H01L21/463

摘要： A slurry contains MnO.sub.2 or other manganese oxide as a primary component of abrasive particles. Further, a polishing process using such a manganese oxide abrasive and a fabrication process of a semiconductor device using such a polishing process are disclosed.

摘要翻译： 浆料含有MnO 2或其它氧化锰作为磨料颗粒的主要成分。 此外，公开了使用这种氧化锰研磨剂的研磨工艺和使用这种抛光工艺的半导体器件的制造工艺。

公开(公告)号：US5763325A

公开(公告)日：1998-06-09

申请号：US674507

申请日：1996-07-02

申请人： Sadahiro Kishii ,  Akiyoshi Hatada ,  Rintaro Suzuki ,  Hiroshi Horie ,  Yoshihiro Arimoto ,  Ko Nakamura

发明人： Sadahiro Kishii ,  Akiyoshi Hatada ,  Rintaro Suzuki ,  Hiroshi Horie ,  Yoshihiro Arimoto ,  Ko Nakamura

IPC分类号： C09G1/02 ,  C09K3/14 ,  H01L21/3105 ,  H01L21/463

CPC分类号： H01L21/31053 ,  C09G1/02 ,  C09K3/1463 ,  H01L21/463

摘要： A slurry contains MnO.sub.2 or other manganese oxide as a primary component of abrasive particles. Further, a polishing process using such a manganese oxide abrasive and a fabrication process of a semiconductor device using such a polishing process are disclosed.

摘要翻译： 浆料含有MnO 2或其它氧化锰作为磨料颗粒的主要成分。 此外，公开了使用这种氧化锰研磨剂的研磨工艺和使用这种抛光工艺的半导体器件的制造工艺。

公开(公告)号：US20130248930A1

公开(公告)日：2013-09-26

申请号：US13894871

申请日：2013-05-15

申请人： Yosuke Shimamune ,  Akira Katakami ,  Akiyoshi Hatada ,  Masashi Shima ,  Naoyoshi Tamura

发明人： Yosuke Shimamune ,  Akira Katakami ,  Akiyoshi Hatada ,  Masashi Shima ,  Naoyoshi Tamura

IPC分类号： H01L29/78

CPC分类号： H01L29/7848 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28518 ,  H01L21/30608 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/45 ,  H01L29/4975 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  Y10S257/90

摘要： A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.

公开(公告)号：US08207042B2

公开(公告)日：2012-06-26

申请号：US12564313

申请日：2009-09-22

申请人： Yosuke Shimamune ,  Masahiro Fukuda ,  Young Suk Kim ,  Akira Katakami ,  Akiyoshi Hatada ,  Naoyoshi Tamura ,  Hiroyuki Ohta

发明人： Yosuke Shimamune ,  Masahiro Fukuda ,  Young Suk Kim ,  Akira Katakami ,  Akiyoshi Hatada ,  Naoyoshi Tamura ,  Hiroyuki Ohta

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.

公开(公告)号：US08164085B2

公开(公告)日：2012-04-24

申请号：US12916953

申请日：2010-11-01

申请人： Yosuke Shimamune ,  Hiroyuki Ohta ,  Akiyoshi Hatada ,  Akira Katakami ,  Naoyoshi Tamura

发明人： Yosuke Shimamune ,  Hiroyuki Ohta ,  Akiyoshi Hatada ,  Akira Katakami ,  Naoyoshi Tamura

IPC分类号： H01L29/06

CPC分类号： H01L29/165 ,  H01L29/045 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.

摘要翻译： 公开了一种制造半导体器件的方法，其能够抑制短沟道效应并改善载流子迁移率。 在该方法中，在对应于源极区和漏极区的硅衬底中形成沟槽。 当外延生长p型半导体混晶层以填充沟槽时，沟槽的表面被刻面划分，半导体混晶层的延伸部分形成在第二侧壁绝缘膜的底表面和 硅衬底和延伸部分与源极延伸区域和漏极延伸区域接触。