公开(公告)号：US08744324B2

公开(公告)日：2014-06-03

申请号：US13175001

申请日：2011-07-01

申请人： Yoshihisa Mizumoto ,  Akihiko Kawatani ,  Takashi Marui ,  Kenichi Kuroda

发明人： Yoshihisa Mizumoto ,  Akihiko Kawatani ,  Takashi Marui ,  Kenichi Kuroda

IPC分类号： G03G15/08

CPC分类号： G03G15/0818 ,  G03G2215/0634

摘要： The semiconductive roller according to the present invention includes a roller body having an outer peripheral surface made of a crosslinked substance of a semiconductive rubber composition and exhibiting Shore A hardness of not more than 60, the semiconductive rubber composition contains a base polymer made of a mixture of (1) mixed rubber N of liquid nitrile rubber and solid nitrile rubber, (2) chloroprene rubber C, and (3) epichlorohydrin rubber E in a mass ratio (C+E)/N of 10/90 to 80/20, the ratios of the chloroprene rubber and the epichlorohydrin rubber in the total quantity of the base polymer are not less than 5 mass % and not less than 5 mass % respectively, and roller resistance at an applied voltage of 5 V is not less than 104Ω and not more than 109Ω.

摘要翻译： 根据本发明的半导电辊包括：具有由半导体橡胶组合物的交联物质制成的外周表面并且肖氏A硬度不大于60的辊体，所述半导体橡胶组合物含有由混合物制成的基础聚合物 的（1）混合橡胶N为液态丁腈橡胶和固体丁腈橡胶，（2）氯丁二烯橡胶C和（3）表氯醇橡胶E的质量比（C + E）/ N为10/90〜80/20， 氯丁橡胶和表氯醇橡胶在基础聚合物总量中的比例分别不低于5质量％且不小于5质量％，施加电压为5V时的辊电阻不小于104＆OHgr; 不超过109＆OHgr。

公开(公告)号：US09075340B2

公开(公告)日：2015-07-07

申请号：US13494696

申请日：2012-06-12

申请人： Kenichi Kuroda ,  Akihiko Kawatani ,  Yoshihisa Mizumoto

发明人： Kenichi Kuroda ,  Akihiko Kawatani ,  Yoshihisa Mizumoto

IPC分类号： G03G15/08 ,  G03G13/20

CPC分类号： G03G15/0818 ,  G03G13/20 ,  G03G2215/0861

摘要： An inventive developing roller is adapted for use in an electrophotographic image forming apparatus. The developing roller includes a roller body. At least an outer peripheral surface of the roller body is formed from a rubber composition containing a base rubber. The base rubber contains a styrene butadiene rubber in a proportion of not less than 10 mass % and not greater than 70 mass % based on the overall amount of the base rubber. The outer peripheral surface of the rubber body has a surface roughness Ra of not less than 0.78 μm and not greater than 1.8 μm.

摘要翻译： 本发明的显影辊适用于电子照相成像设备。 显影辊包括辊体。 辊体的至少外周面由含有基础橡胶的橡胶组合物形成。 基础橡胶含有基于橡胶总量不小于10质量％且不大于70质量％的丁苯橡胶。 橡胶体的外周面的表面粗糙度Ra为0.78μm以上且1.8μm以下。

公开(公告)号：US08670700B2

公开(公告)日：2014-03-11

申请号：US13559987

申请日：2012-07-27

申请人： Kenichi Kuroda ,  Akihiko Kawatani ,  Masakazu Tanaka ,  Yoshihisa Mizumoto

发明人： Kenichi Kuroda ,  Akihiko Kawatani ,  Masakazu Tanaka ,  Yoshihisa Mizumoto

IPC分类号： G03G15/08

CPC分类号： G03G15/0818

摘要： A developing roller is provided, which is particularly used in an image forming apparatus of a highly durable design and is free from toner leakage even after formation of a predetermined number of images. Opposite end regions (5a) of an outer peripheral surface (5) of a roller body (2) of the developing roller (1) to be respectively kept in sliding contact with seal members each have a friction coefficient μ of not greater than 0.15.

摘要翻译： 提供了一种显影辊，其特别用于高度耐用设计的图像形成装置中，即使在形成预定数量的图像之后也不会有调色剂泄漏。 与密封件分别保持滑动接触的显影辊（1）的辊体（2）的外周面（5）的相对的端部区域（5a）各自具有不大于0.15的摩擦系数μ。

公开(公告)号：US09059193B2

公开(公告)日：2015-06-16

申请号：US13514201

申请日：2010-12-27

申请人： Kenichi Ohtsuka ,  Kenichi Kuroda ,  Hiroshi Watanabe ,  Naoki Yutani ,  Hiroaki Sumitani

发明人： Kenichi Ohtsuka ,  Kenichi Kuroda ,  Hiroshi Watanabe ,  Naoki Yutani ,  Hiroaki Sumitani

IPC分类号： H01L29/15 ,  H01L29/66 ,  C30B23/02 ,  C30B25/02 ,  C30B29/36 ,  H01L21/02 ,  H01L29/10 ,  H01L29/16 ,  H01L29/872 ,  H01L21/04 ,  H01L29/78

CPC分类号： H01L29/66068 ,  C30B23/02 ,  C30B25/02 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/02496 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/0495 ,  H01L29/107 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/872

摘要： A silicon carbide semiconductor element, including: i) an n-type silicon carbide substrate doped with a dopant, such as nitrogen, at a concentration C, wherein the substrate has a lattice constant that decreases with doping; ii) an n-type silicon carbide epitaxially-grown layer doped with the dopant, but at a smaller concentration than the substrate; and iii) an n-type buffer layer doped with the dopant, and arranged between the substrate and the epitaxially-grown layer, wherein the buffer layer has a multilayer structure in which two or more layers having the same thickness are laminated, and is configured such that, based on a number of layers (N) in the multilayer structure, a doping concentration of a K-th layer from a silicon carbide epitaxially-grown layer side is C·K/(N+1).

摘要翻译： 一种碳化硅半导体元件，包括：i）以浓度C掺杂有诸如氮的掺杂剂的n型碳化硅衬底，其中所述衬底具有随着掺杂而降低的晶格常数; ii）掺杂有掺杂剂但以比衬底更小的浓度的n型碳化硅外延生长层; 并且iii）掺杂有掺杂剂的n型缓冲层，并且布置在所述衬底和所述外延生长层之间，其中所述缓冲层具有其中层叠具有相同厚度的两层或更多层的多层结构，并且被配置 使得基于多层结构中的多个层（N），来自碳化硅外延生长层的第K层的掺杂浓度为C·K /（N + 1）。

公开(公告)号：US08569123B2

公开(公告)日：2013-10-29

申请号：US13258941

申请日：2009-09-01

申请人： Yoshinori Matsuno ,  Kenichi Ohtsuka ,  Naoki Yutani ,  Kenichi Kuroda ,  Hiroshi Watanabe ,  Shozo Shikama

发明人： Yoshinori Matsuno ,  Kenichi Ohtsuka ,  Naoki Yutani ,  Kenichi Kuroda ,  Hiroshi Watanabe ,  Shozo Shikama

IPC分类号： H01L21/338

CPC分类号： H01L21/046 ,  H01L21/0495 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/872

摘要： An object is to provide a method for manufacturing a silicon carbide semiconductor device in which a time required for removing a sacrificial oxide film can be shortened and damage to a surface of the silicon carbide layer can be reduced. The method for manufacturing a silicon carbide semiconductor device includes: (a) performing ion implantation to a silicon carbide layer; (b) performing activation annealing to the ion-implanted silicon carbide layer 2; (c) removing a surface layer of the silicon carbide layer 2, to which the activation annealing has been performed, by dry etching; (d) forming a sacrificial oxide film on a surface layer of the silicon carbide layer, to which the dry etching has been performed, by performing sacrificial oxidation thereto; and (e) removing the sacrificial oxide film by wet etching.

摘要翻译： 本发明的目的是提供一种用于制造碳化硅半导体器件的方法，其中可以缩短去除牺牲氧化膜所需的时间，并且可以降低对碳化硅层的表面的损坏。 制造碳化硅半导体器件的方法包括：（a）对碳化硅层进行离子注入; （b）对离子注入碳化硅层2进行激活退火; （c）通过干蚀刻去除已经进行了活化退火的碳化硅层2的表面层; （d）通过对其进行牺牲氧化，在已经进行了干蚀刻的碳化硅层的表面层上形成牺牲氧化膜; 和（e）通过湿蚀刻去除牺牲氧化膜。

公开(公告)号：US20120241766A1

公开(公告)日：2012-09-27

申请号：US13514201

申请日：2010-12-27

申请人： Kenichi Ohtsuka ,  Kenichi Kuroda ,  Hiroshi Watanabe ,  Naoki Yutani ,  Hiroaki Sumitani

发明人： Kenichi Ohtsuka ,  Kenichi Kuroda ,  Hiroshi Watanabe ,  Naoki Yutani ,  Hiroaki Sumitani

IPC分类号： H01L29/167

CPC分类号： H01L29/66068 ,  C30B23/02 ,  C30B25/02 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/02496 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/0495 ,  H01L29/107 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/872

摘要： A silicon carbide semiconductor element, including: i) an n-type silicon carbide substrate doped with a dopant, such as nitrogen, at a concentration C, wherein the substrate has a lattice constant that decreases with doping; ii) an n-type silicon carbide epitaxially-grown layer doped with the dopant, but at a smaller concentration than the substrate; and iii) an n-type buffer layer doped with the dopant, and arranged between the substrate and the epitaxially-grown layer, wherein the buffer layer has a multilayer structure in which two or more layers having the same thickness are laminated, and is configured such that, based on a number of layers (N) in the multilayer structure, a doping concentration of a K-th layer from a silicon carbide epitaxially-grown layer side is C·K/(N+1).

摘要翻译： 一种碳化硅半导体元件，包括：i）以浓度C掺杂有诸如氮的掺杂剂的n型碳化硅衬底，其中所述衬底具有随着掺杂而降低的晶格常数; ii）掺杂有掺杂剂但以比衬底更小的浓度的n型碳化硅外延生长层; 并且iii）掺杂有掺杂剂的n型缓冲层，并且布置在所述衬底和所述外延生长层之间，其中所述缓冲层具有其中层叠具有相同厚度的两层或更多层的多层结构，并且被配置 使得基于多层结构中的多个层（N），来自碳化硅外延生长层的第K层的掺杂浓度为C·K /（N + 1）。

公开(公告)号：US08119495B2

公开(公告)日：2012-02-21

申请号：US13096246

申请日：2011-04-28

申请人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

发明人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

IPC分类号： H01L21/76

CPC分类号： H01L23/5283 ,  H01L21/31053 ,  H01L21/74 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/4925 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.

摘要翻译： 提供了一种用于改善嵌入在多个凹部中的构件的表面处的平坦度而不导致制造过程所需时间增加的技术。 根据该技术，通过将相对较宽区域的第一伪图案DP1和相对较小面积的第二虚设图案DP2放置在元件形成区域DA和虚拟区域FA之间的边界BL附近的虚拟图案， 在虚拟区域FA中。 由此，可以在虚拟区域FA的整个部分改善嵌入在隔离槽内的氧化硅膜的表面的平坦度。 此外，当第一伪图案DP1占据虚拟区域FA中相对较宽的区域时，可以控制掩模数据的增加。

公开(公告)号：US07948086B2

公开(公告)日：2011-05-24

申请号：US12714596

申请日：2010-03-01

申请人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

发明人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

IPC分类号： H01L23/48

CPC分类号： H01L23/5283 ,  H01L21/31053 ,  H01L21/74 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/4925 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.

摘要翻译： 提供了一种用于改善嵌入在多个凹部中的构件的表面处的平坦度而不导致制造过程所需时间增加的技术。 根据该技术，通过将相对较宽区域的第一伪图案DP1和相对较小面积的第二虚设图案DP2放置在元件形成区域DA和虚拟区域FA之间的边界BL附近的虚拟图案， 在虚拟区域FA中。 由此，可以在虚拟区域FA的整个部分改善嵌入在隔离槽内的氧化硅膜的表面的平坦度。 此外，当第一伪图案DP1占据虚拟区域FA中相对较宽的区域时，可以控制掩模数据的增加。

公开(公告)号：US07589423B2

公开(公告)日：2009-09-15

申请号：US11802623

申请日：2007-05-24

申请人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

发明人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

IPC分类号： H01L23/48

CPC分类号： H01L23/5283 ,  H01L21/31053 ,  H01L21/74 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/4925 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.

摘要翻译： 提供了一种用于改善嵌入在多个凹部中的构件的表面处的平坦度而不导致制造过程所需时间增加的技术。 根据该技术，通过将相对较宽区域的第一伪图案DP1和相对较小面积的第二虚设图案DP2放置在元件形成区域DA和虚拟区域FA之间的边界BL附近的虚拟图案， 在虚拟区域FA中。 由此，可以在虚拟区域FA的整个部分改善嵌入在隔离槽内的氧化硅膜的表面的平坦度。 此外，当第一伪图案DP1占据虚拟区域FA中相对较宽的区域时，可以控制掩模数据的增加。

公开(公告)号：US07411302B2

公开(公告)日：2008-08-12

申请号：US11430983

申请日：2006-05-10

申请人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

发明人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

IPC分类号： H01L23/48

CPC分类号： H01L23/5283 ,  H01L21/31053 ,  H01L21/74 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/4925 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.